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ethernet
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WIP 100BASE-TX PHY
86 Commits 2 Branches 0 Tags 290 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
SystemVerilog 0.8%
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Sean Anderson be2bded61e Add some more files to gitignore 
Some of the ignores were not updated properly when reworking the
Makefile. Also add tags.

Fixes: 6af697b ("Initial support for post-placement simulation")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2022-11-05 12:52:57 -04:00
LICENSES Add licenses 2022-11-05 12:50:12 -04:00
rtl Add phy_core 2022-11-05 12:37:18 -04:00
tb Add phy_core 2022-11-05 12:37:18 -04:00
.gitignore Add some more files to gitignore 2022-11-05 12:52:57 -04:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
CONTRIBUTING Add licenses 2022-11-05 12:50:12 -04:00
COPYING Add licenses 2022-11-05 12:50:12 -04:00
Makefile Fix building tests 2022-11-05 12:37:18 -04:00