b68e1312c4
This adds a basic clause 27 repeater (hub), mostly for test purposes. It's effectively just the state machine in figure 27-4 and nothing else (e.g. no partitioning or jabber detection). This is surprisingly simple. Unfortunately, yosys doesn't allow memories in port declarations, even for systemverilog. This complicates the implementation and testbench, since we have to do the slicing ourselves. This is particularly awful for the testbench, since module.signal[0].value != module.signal.value[0] and module.signal can't be indexed by slices, and module.signal.value is big endian (ugh ugh ugh). There is no clean solution here. Signed-off-by: Sean Anderson <seanga2@gmail.com> |
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| LICENSES | ||
| lib | ||
| rtl | ||
| tb | ||
| .gitignore | ||
| .gitmodules | ||
| 4b5b.gtkw | ||
| CONTRIBUTING | ||
| COPYING | ||
| Makefile | ||