195 lines
4.1 KiB
Verilog
195 lines
4.1 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*
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* This roughly follows the design of XAPP225. However, we use a 2x rate DDR
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* clock instead of two clocks 90 degrees out of phase. Yosys/nextpnr cannot
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* guarantee the phase relationship of any clocks, even those from the same
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* PLL. Because of this, we assume that clk_250 and clk_125 are unrelated.
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*/
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`include "common.vh"
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`include "io.vh"
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`timescale 1ns/1ps
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module pmd_dp83223_rx (
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input clk_250,
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input clk_125,
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input signal_detect,
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input indicate_data,
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/* PMD */
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output signal_status,
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output reg [1:0] rx_data,
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output reg [1:0] rx_data_valid
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);
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reg [1:0] rx_p, rx_n;
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reg [4:0] sd_delay;
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initial sd_delay[4:0] = 5'b0;
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`ifdef SYNTHESIS
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SB_IO #(
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.PIN_TYPE(`PIN_OUTPUT_NEVER | `PIN_INPUT_DDR),
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) rx_data_pin (
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.PACKAGE_PIN(indicate_data),
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.INPUT_CLK(clk_250),
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.D_IN_0(rx_p[0]),
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.D_IN_1(rx_n[0])
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);
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`else
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always @(posedge clk_250)
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rx_p[0] <= indicate_data;
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always @(negedge clk_250)
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rx_n[0] <= indicate_data;
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`endif
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/*
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* Delay signal status until the known good data has had a chance to
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* make it through the pipeline. This isn't necessary for real hardware
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* (since signal status is asserted long after we have good data), but
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* it helps out during simulation. It also helps avoid metastability.
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*/
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always @(posedge clk_125)
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sd_delay[4:0] <= { sd_delay[3:0], signal_detect };
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assign signal_status = sd_delay[4];
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/*
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* Get things into the clk_250 domain so that we sample posedge before
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* negedge. Without this we can have a negedge which happens before the
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* posedge.
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*/
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always @(posedge clk_250) begin
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rx_p[1] <= rx_p[0];
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rx_n[1] <= rx_n[0];
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end
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reg [3:0] rx_a, rx_b, rx_c, rx_d;
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/* Get everything in the clk_125 domain */
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always @(posedge clk_125) begin
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rx_a[0] <= rx_p[1];
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rx_b[0] <= rx_n[1];
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end
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always @(negedge clk_125) begin
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rx_c[0] <= rx_p[1];
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rx_d[0] <= rx_n[1];
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end
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/*
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* Buffer things a bit. We wait a cycle to avoid metastability. After
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* that, we need two cycles of history to detect edges, plus a final
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* cycle to select from.
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*/
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always @(posedge clk_125) begin
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rx_a[3:1] <= rx_a[2:0];
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rx_b[3:1] <= rx_b[2:0];
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rx_c[3:1] <= rx_c[2:0];
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rx_d[3:1] <= rx_d[2:0];
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end
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localparam A = 0;
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localparam B = 1;
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localparam C = 2;
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localparam D = 3;
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reg [1:0] state, state_next;
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initial state = A;
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reg valid, valid_next;
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reg wraparound, wraparound_next;
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initial valid = 0;
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reg [1:0] rx_data_next, rx_data_valid_next;
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reg [3:0] rx_r, rx_f;
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always @(*) begin
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rx_r = {
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rx_a[1] & ~rx_a[2],
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rx_b[1] & ~rx_b[2],
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rx_c[1] & ~rx_c[2],
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rx_d[1] & ~rx_d[2]
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};
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rx_f = {
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~rx_a[1] & rx_a[2],
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~rx_b[1] & rx_b[2],
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~rx_c[1] & rx_c[2],
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~rx_d[1] & rx_d[2]
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};
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state_next = state;
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valid_next = 1;
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wraparound_next = 0;
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if (rx_r == 4'b1111 || rx_f == 4'b1111) begin
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state_next = C;
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end else if (rx_r == 4'b1000 || rx_f == 4'b1000) begin
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state_next = D;
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wraparound_next = state == A;
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end else if (rx_r == 4'b1100 || rx_f == 4'b1100) begin
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state_next = A;
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wraparound_next = state == D;
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end else if (rx_r == 4'b1110 || rx_f == 4'b1110) begin
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state_next = B;
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end else begin
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valid_next = valid;
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end
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if (!signal_status) begin
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state_next = A;
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valid_next = 0;
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end
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rx_data_next[0] = rx_d[3];
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rx_data_valid_next = 1;
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case (state)
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A: begin
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rx_data_next[1] = rx_a[3];
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rx_data_valid_next = !wraparound;
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end
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B: begin
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rx_data_next[1] = rx_b[3];
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end
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C: begin
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rx_data_next[1] = rx_c[3];
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end
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D: begin
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rx_data_next[1] = rx_d[3];
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if (wraparound) begin
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rx_data_next[1] = rx_a[3];
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rx_data_valid_next = 2;
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end
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end
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endcase
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if (!valid_next)
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rx_data_valid_next = 0;
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end
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always @(posedge clk_125) begin
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state <= state_next;
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valid <= valid_next;
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wraparound <= wraparound_next;
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rx_data <= rx_data_next;
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rx_data_valid <= rx_data_valid_next;
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end
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`ifndef SYNTHESIS
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reg [255:0] state_text;
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wire [13:0] delay;
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always @(*) begin
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case (state)
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A: state_text = "A";
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B: state_text = "B";
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C: state_text = "C";
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D: state_text = "D";
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endcase
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end
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`endif
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endmodule
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