WIP 100BASE-TX PHY
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Sean Anderson 7c9ac42988 Add wishbone mux
This adds a simple wishbone mux. The idea is that each slave gets its
own address bit. This lends itself to extemely simple address decoding,
but uses up address space quickly. In theory, we could also give larger
addres space to some slaves, but currently lower bits have priority. The
testbench is also very simple. Since everything is combinatorial, we can
determine the outputs from the inputs exactly.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-02-18 22:48:36 -05:00
LICENSES Add LFSR 2023-01-09 21:01:27 -05:00
lib Add LFSR 2023-01-09 21:01:27 -05:00
rtl Add wishbone mux 2023-02-18 22:48:36 -05:00
tb Add wishbone mux 2023-02-18 22:48:36 -05:00
.gitignore Add some more files to gitignore 2022-11-05 12:52:57 -04:00
.gitmodules Add LFSR 2023-01-09 21:01:27 -05:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
CONTRIBUTING Add licenses 2022-11-05 12:50:12 -04:00
COPYING Add licenses 2022-11-05 12:50:12 -04:00
Makefile Add wishbone mux 2023-02-18 22:48:36 -05:00