79 lines
1.5 KiB
Verilog
79 lines
1.5 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*
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* 8n1@115200; no one uses anything else (and neither do I)
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*/
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`include "common.vh"
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module uart_tx (
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input clk, rst,
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input [7:0] data,
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output reg ready,
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input valid,
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output reg tx,
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/* Run at 4M for testing */
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input high_speed
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);
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/* 1085 cycles, for 115200 baud with a 125 MHz clock */
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parameter SLOW_VALUE = 11'h78c;
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/* 31 cycles, for 4M baud with a 125 MHz clock */
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parameter FAST_VALUE = 11'h68e;
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reg [7:0] data_last;
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reg valid_last, ready_next;
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reg [10:0] lfsr, lfsr_next;
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reg [3:0] counter, counter_next;
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reg [8:0] bits, bits_next;
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always @(*) begin
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tx = bits[0];
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ready_next = ready;
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counter_next = counter;
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lfsr_next = { lfsr[9:0], lfsr[10] ^ lfsr[8] };
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bits_next = bits;
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if (&lfsr) begin
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if (counter)
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counter_next = counter - 1;
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else
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ready_next = 1;
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lfsr_next = high_speed ? FAST_VALUE : SLOW_VALUE;
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bits_next = { 1'b1, bits[8:1] };
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end
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if (valid_last && ready) begin
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ready_next = 0;
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counter_next = 9;
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lfsr_next = high_speed ? FAST_VALUE : SLOW_VALUE;
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bits_next = { data_last, 1'b0 };
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end
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end
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always @(posedge clk) begin
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data_last <= data;
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counter <= counter_next;
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lfsr <= lfsr_next;
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end
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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ready <= 1'b1;
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valid_last <= 1'b0;
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bits <= 9'h1ff;
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end else begin
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ready <= ready_next;
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valid_last <= valid;
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bits <= bits_next;
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end
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end
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endmodule
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