27 lines
432 B
Verilog
27 lines
432 B
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module scramble (
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input clk,
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input unscrambled,
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output reg scrambled
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);
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reg lfsr_next;
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reg [10:0] lfsr;
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initial lfsr = 11'h7ff;
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always @(*) begin
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lfsr_next = lfsr[8] ^ lfsr[10];
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scrambled = unscrambled ^ lfsr_next;
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end
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always @(posedge clk)
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lfsr <= { lfsr[9:0], lfsr_next };
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endmodule
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