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ethernet
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WIP 100BASE-TX PHY
137 Commits 2 Branches 0 Tags 285 KiB
Verilog 50.1%
Python 46.8%
Makefile 2.3%
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Sean Anderson 165b60b7b2 Makefile: Add some missing modules 
Add some modules to test with which were previously missing.

Fixes: b68e131 ("Add a basic hub")
Fixes: 0495ae3 ("Add TX MAC (most of it)")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 		2023-02-20 23:34:10 -05:00
LICENSES Add LFSR 2023-01-09 21:01:27 -05:00
examples Add examples 2023-02-20 23:34:10 -05:00
lib Add LFSR 2023-01-09 21:01:27 -05:00
rtl Add examples 2023-02-20 23:34:10 -05:00
tb Add hub 2023-02-20 23:34:10 -05:00
.gitignore Add .bin to file extensions 2023-02-20 23:34:10 -05:00
.gitmodules Add LFSR 2023-01-09 21:01:27 -05:00
4b5b.gtkw Initial commit 2022-05-23 20:57:03 -04:00
CONTRIBUTING Add licenses 2022-11-05 12:50:12 -04:00
COPYING Add licenses 2022-11-05 12:50:12 -04:00
Makefile Makefile: Add some missing modules 2023-02-20 23:34:10 -05:00