45 lines
617 B
Verilog
45 lines
617 B
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module top (
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input SYSCLK,
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input [1:0] BUT,
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output [1:0] LED
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);
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parameter WISHBONE = 1;
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wire clk_125;
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SB_PLL40_CORE #(
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.FEEDBACK_PATH("SIMPLE"),
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.DIVR(4'd0),
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.DIVF(7'd9),
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.DIVQ(3'd3),
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.FILTER_RANGE(3'd5),
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) pll (
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.REFERENCECLK(SYSCLK),
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.PLLOUTGLOBAL(clk_125),
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.BYPASS(1'b0),
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.RESETB(1'b1)
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);
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wire [1:0] led_n;
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assign LED = ~led_n;
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led_blinker #(
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.LEDS(2)
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) blinker(
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.clk(clk_125),
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.triggers(~BUT),
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.out(led_n),
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.test_mode(1'b0)
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);
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endmodule
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