53 lines
1.0 KiB
Verilog
53 lines
1.0 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module wb_reg (
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input clk, rst,
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output reg s_ack, s_err,
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input s_cyc, s_stb, s_we,
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input [ADDR_WIDTH - 1:0] s_addr,
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input [DATA_WIDTH - 1:0] s_data_write,
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output reg [DATA_WIDTH - 1:0] s_data_read,
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input m_ack, m_err,
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output reg m_cyc, m_stb, m_we,
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output reg [ADDR_WIDTH - 1:0] m_addr,
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output reg [DATA_WIDTH - 1:0] m_data_write,
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input [DATA_WIDTH - 1:0] m_data_read
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);
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parameter ADDR_WIDTH = 16;
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parameter DATA_WIDTH = 16;
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initial begin
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s_ack = 0;
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s_err = 0;
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m_cyc = 0;
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m_stb = 0;
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end
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always @(posedge clk) begin
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if (rst) begin
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s_ack <= 0;
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s_err <= 0;
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m_cyc <= 0;
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m_stb <= 0;
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end else begin
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s_ack <= m_ack && s_cyc && s_stb;
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s_err <= m_err && s_cyc && s_stb;
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m_cyc <= s_cyc && !(m_ack || m_err);
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m_stb <= s_stb && !(m_ack || m_err);
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end
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s_data_read <= m_data_read;
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m_we <= s_we;
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m_addr <= s_addr;
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m_data_write <= s_data_write;
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end
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endmodule
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