82 lines
1.4 KiB
Verilog
82 lines
1.4 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module uart_wb_bridge (
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input clk,
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input rst,
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/* UART */
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input rx,
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output tx,
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/* Wishbone */
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output wb_rst,
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input wb_ack, wb_err,
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output wb_cyc, wb_stb, wb_we,
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output [ADDR_WIDTH - 1:0] wb_addr,
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output [DATA_WIDTH - 1:0] wb_data_write,
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input [DATA_WIDTH - 1:0] wb_data_read,
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input high_speed
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);
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parameter ADDR_WIDTH = 16;
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localparam DATA_WIDTH = 16;
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wire rx_ready, rx_valid;
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wire [7:0] rx_data;
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wire overflow;
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uart_rx uart_rx (
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.clk(clk),
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.rst(rst),
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.rx(rx),
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.ready(rx_ready),
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.valid(rx_valid),
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.data(rx_data),
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.high_speed(high_speed),
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.overflow(overflow),
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.frame_error(wb_rst)
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);
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wire tx_ready, tx_valid;
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wire [7:0] tx_data;
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axis_wb_bridge #(
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.ADDR_WIDTH(ADDR_WIDTH)
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) bridge (
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.clk(clk),
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.rst(rst || wb_rst),
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.s_axis_ready(rx_ready),
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.s_axis_valid(rx_valid),
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.s_axis_data(rx_data),
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.m_axis_ready(tx_ready),
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.m_axis_valid(tx_valid),
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.m_axis_data(tx_data),
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.wb_ack(wb_ack),
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.wb_err(wb_err),
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.wb_cyc(wb_cyc),
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.wb_stb(wb_stb),
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.wb_we(wb_we),
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.wb_addr(wb_addr),
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.wb_data_write(wb_data_write),
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.wb_data_read(wb_data_read),
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.overflow(overflow)
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);
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uart_tx uart_tx (
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.clk(clk),
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.rst(rst),
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.tx(tx),
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.ready(tx_ready),
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.valid(tx_valid),
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.data(tx_data),
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.high_speed(high_speed)
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);
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endmodule
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