24 lines
343 B
Verilog
24 lines
343 B
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module nrzi_encode (
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input clk,
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input nrz,
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output reg nrzi
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);
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reg nrzi_next;
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initial nrzi = 1;
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always @(*)
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nrzi_next = nrz ^ nrzi;
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always @(posedge clk)
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nrzi <= nrzi_next;
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endmodule
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