60 lines
1.2 KiB
Verilog
60 lines
1.2 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module nrzi_decode (
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input clk,
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input rst,
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input [1:0] nrzi,
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input [1:0] nrzi_valid,
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output reg [1:0] nrz,
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output reg [1:0] nrz_valid
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);
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reg [1:0] nrz_next, nrz_valid_next;
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reg nrzi_last, nrzi_last_next, nrzi_last_valid, nrzi_last_valid_next;
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initial nrz_valid = 0;
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initial nrzi_last_valid = 0;
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always @(*) begin
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nrz_next[0] = nrzi[1] ^ nrzi[0];
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nrz_next[1] = nrzi[1] ^ nrzi_last;
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nrzi_last_next = nrzi_last;
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nrzi_last_valid_next = 1'b1;
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if (nrzi_valid[1])
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nrzi_last_next = nrzi[0];
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else if (nrzi_valid[0])
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nrzi_last_next = nrzi[1];
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else
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nrzi_last_valid_next = nrzi_last_valid;
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nrz_valid_next = nrzi_valid;
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if (!nrzi_last_valid) begin
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nrz_valid_next = 0;
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if (nrzi_valid[1]) begin
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nrz_valid_next = 2'b1;
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nrz_next[1] = nrz_next[0];
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end
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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nrzi_last <= 1'bX;
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nrzi_last_valid <= 1'b0;
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nrz_valid <= 2'b0;
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nrz <= 2'b0;
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end else begin
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nrzi_last <= nrzi_last_next;
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nrzi_last_valid = nrzi_last_valid_next;
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nrz_valid <= nrz_valid_next;
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nrz <= nrz_next;
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end
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end
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endmodule
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