298 lines
7.5 KiB
Verilog
298 lines
7.5 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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`include "common.vh"
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module mdio_regs (
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/* Wishbone */
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input clk,
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output reg ack, err,
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input cyc, stb, we,
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input [4:0] addr,
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input [15:0] data_write,
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output reg [15:0] data_read,
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/* Control signals */
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input link_status,
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input positive_wraparound,
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input negative_wraparound,
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input false_carrier,
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input symbol_error,
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output reg loopback,
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output reg pdown,
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output reg isolate,
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output reg coltest,
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output reg descrambler_test,
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output reg link_monitor_test
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);
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/*
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* A test OUI in "canonical" form. Don't use this! It's just here to
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* test the bit-reversal logic (as seen in 802 8.2.2).
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*/
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parameter [23:0] OUI = 24'hacde48;
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parameter [5:0] MODEL = 0;
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parameter [3:0] REVISION = 0;
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/*
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* Normally, this module will assert err when read/writing to an
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* unknown register. The master will detect this and won't drive the
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* MDIO line. However, this might be undesirable if there is no
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* external MDIO bus. Setting this parameter to 0 will cause it to ack
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* all transactions. Writes to unknown registers will be ignored, and
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* reads from unknown registers will yield 16'hffff, emulating
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* a pull-up on MDIO.
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*/
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parameter EMULATE_PULLUP = 0;
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/* Enable counter registers */
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parameter ENABLE_COUNTERS = 1;
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/*
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* Number of bits in counters; we can't meet timing with 16 bits, so
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* use a smaller default.
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*/
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parameter COUNTER_WIDTH = 15;
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/* c22 Basic Mode Control Register */
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localparam BMCR = 0;
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/* c22 Basic Mode Status Register */
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localparam BMSR = 1;
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/* c22 Phy Identifier */
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localparam ID1 = 2;
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localparam ID2 = 3;
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/* Negative Wraparound Counter Register */
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localparam NWCR = 16;
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/* Positive Wraparound Counter Register */
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localparam PWCR = 17;
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/* Disconnect Counter Register */
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localparam DCR = 18;
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/* False Carrier Counter Register */
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localparam FCCR = 19;
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/* Symbol Error Counter Register */
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localparam SECR = 21;
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/* Vendor Control Register */
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localparam VCR = 30;
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localparam BMCR_RESET = 15;
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localparam BMCR_LOOPBACK = 14;
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localparam BMCR_SPEED_LSB = 13;
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localparam BMCR_PDOWN = 11;
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localparam BMCR_ISOLATE = 10;
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localparam BMCR_DUPLEX = 8;
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localparam BMCR_COLTEST = 7;
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localparam BMCR_SPEED_MSB = 6;
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localparam BMSR_100FULL = 14;
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localparam BMSR_100HALF = 13;
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localparam BMSR_LSTATUS = 2;
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localparam BMSR_EXTCAP = 0;
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/* VCR Descrambler test mode */
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localparam VCR_DTEST = 15;
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/* VCR Link monitor test mode */
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localparam VCR_LTEST = 14;
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integer i;
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reg ack_next, err_next;
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reg [15:0] data_read_next;
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reg duplex, link_status_latched, link_status_latched_next, link_status_last, disconnect;
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reg loopback_next, pdown_next, isolate_next, duplex_next, coltest_next;
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reg descrambler_test_next, link_monitor_test_next;
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reg nwl, pwl, dl, fcl, sel;
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/* Can't meet timing at 16 bits wide */
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reg [COUNTER_WIDTH-1:0] nwc, pwc, dc, fcc, sec;
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reg [COUNTER_WIDTH-1:0] nwc_next, pwc_next, dc_next, fcc_next, sec_next;
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initial begin
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ack = 0;
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err = 0;
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loopback = 0;
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pdown = 0;
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isolate = 1;
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duplex = 0;
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coltest = 0;
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link_status_latched = 0;
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link_status_last = 0;
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if (ENABLE_COUNTERS) begin
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nwl = 0;
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pwl = 0;
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dl = 0;
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fcl = 0;
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sel = 0;
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nwc = 0;
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pwc = 0;
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dc = 0;
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fcc = 0;
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sec = 0;
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end
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descrambler_test = 0;
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link_monitor_test = 0;
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end
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always @(*) begin
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loopback_next = loopback;
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pdown_next = pdown;
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isolate_next = isolate;
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duplex_next = duplex;
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coltest_next = coltest;
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link_status_latched_next = link_status_latched && link_status;
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disconnect = link_status_last && !link_status;
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descrambler_test_next = descrambler_test;
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link_monitor_test_next = link_monitor_test;
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if (ENABLE_COUNTERS) begin
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nwc_next = nwc;
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pwc_next = pwc;
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dc_next = dc;
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fcc_next = fcc;
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sec_next = sec;
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if (!(&nwc)) nwc_next = nwc + nwl;
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if (!(&pwc)) pwc_next = pwc + pwl;
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if (!(&dc)) dc_next = dc + dl;
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if (!(&fcc)) fcc_next = fcc + fcl;
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if (!(&sec)) sec_next = sec + sel;
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end
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data_read_next = 0;
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ack_next = cyc && stb;
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err_next = 0;
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case (addr)
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BMCR: begin
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data_read_next[BMCR_LOOPBACK] = loopback;
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data_read_next[BMCR_SPEED_LSB] = 1; /* 100 Mb/s */
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data_read_next[BMCR_PDOWN] = pdown;
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data_read_next[BMCR_ISOLATE] = isolate;
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data_read_next[BMCR_DUPLEX] = duplex;
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data_read_next[BMCR_COLTEST] = coltest;
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if (ack_next && we) begin
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loopback_next = data_write[BMCR_LOOPBACK];
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pdown_next = data_write[BMCR_PDOWN];
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isolate_next = data_write[BMCR_ISOLATE];
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duplex_next = data_write[BMCR_DUPLEX];
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coltest_next = data_write[BMCR_COLTEST];
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if (data_write[BMCR_RESET]) begin
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loopback_next = 0;
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pdown_next = 0;
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isolate_next = 1;
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duplex_next = 0;
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coltest_next = 0;
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link_status_latched_next = link_status;
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if (ENABLE_COUNTERS) begin
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nwc_next = negative_wraparound;
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pwc_next = positive_wraparound;
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dc_next = disconnect;
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fcc_next = false_carrier;
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sec_next = symbol_error;
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end
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descrambler_test_next = 0;
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link_monitor_test_next = 0;
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end
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end
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end
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BMSR: begin
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data_read_next[BMSR_100FULL] = 1;
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data_read_next[BMSR_100HALF] = 1;
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data_read_next[BMSR_LSTATUS] = link_status_latched;
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data_read_next[BMSR_EXTCAP] = 1;
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if (ack_next && !we)
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link_status_latched_next = link_status;
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end
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ID1: begin
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/* "bit-reverse" the OUI */
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for (i = 6; i < 8; i = i + 1)
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data_read_next[i - 6] = OUI[7 - i];
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for (i = 0; i < 8; i = i + 1)
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data_read_next[i + 2] = OUI[15 - i];
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for (i = 0; i < 6; i = i + 1)
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data_read_next[i + 10] = OUI[23 - i];
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end
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ID2: begin
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data_read_next[3:0] = REVISION;
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data_read_next[9:4] = MODEL;
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for (i = 0; i < 6; i = i + 1)
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data_read_next[i + 10] = OUI[7 - i];
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end
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NWCR: if (ENABLE_COUNTERS) begin
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data_read_next = nwc;
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if (ack_next)
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nwc_next = we ? data_write : negative_wraparound;
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end
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PWCR: if (ENABLE_COUNTERS) begin
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data_read_next = pwc;
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if (ack_next)
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pwc_next = we ? data_write : positive_wraparound;
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end
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DCR: if (ENABLE_COUNTERS) begin
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data_read_next = dc;
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if (ack_next)
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dc_next = we ? data_write : disconnect;
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end
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FCCR: if (ENABLE_COUNTERS) begin
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data_read_next = fcc;
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if (ack_next)
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fcc_next = we ? data_write : false_carrier;
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end
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SECR: if (ENABLE_COUNTERS) begin
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data_read_next = sec;
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if (ack_next)
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sec_next = we ? data_write : symbol_error;
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end
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VCR: begin
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data_read_next[VCR_DTEST] = descrambler_test;
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data_read_next[VCR_LTEST] = link_monitor_test;
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if (ack_next && we) begin
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descrambler_test_next = data_write[VCR_DTEST];
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link_monitor_test_next = data_write[VCR_LTEST];
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end
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end
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default: begin
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if (EMULATE_PULLUP) begin
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data_read_next = 16'hFFFF;
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end else begin
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err_next = ack_next;
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ack_next = 0;
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data_read_next = 16'hXXXX;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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loopback <= loopback_next;
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pdown <= pdown_next;
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isolate <= isolate_next;
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duplex <= duplex_next;
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coltest <= coltest_next;
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link_status_latched <= link_status_latched_next;
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link_status_last <= link_status;
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ack <= ack_next;
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err <= err_next;
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data_read <= data_read_next;
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if (ENABLE_COUNTERS) begin
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nwl <= negative_wraparound;
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pwl <= positive_wraparound;
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dl <= disconnect;
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fcl <= false_carrier;
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sel <= symbol_error;
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nwc <= nwc_next;
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pwc <= pwc_next;
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dc <= dc_next;
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fcc <= fcc_next;
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sec <= sec_next;
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end
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descrambler_test <= descrambler_test_next;
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link_monitor_test <= link_monitor_test_next;
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end
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endmodule
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