70 lines
1.6 KiB
Verilog
70 lines
1.6 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2023 Sean Anderson <seanga2@gmail.com>
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*
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* This is an LED blinker designed to make it easier to monitor internal
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* signals with LEDs. The blinker is active for ~16 and inactive for ~16 ms.
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* When triggered, the corresponding output will go high the next time
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* the blinker becomes active. This results in blinking at 30 Hz if
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* continuously triggered. All outputs blink at the same time.
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*/
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`include "common.vh"
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module led_blinker (
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input clk,
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input [LEDS - 1:0] triggers,
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output reg [LEDS - 1:0] out,
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input test_mode
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);
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parameter LEDS = 2;
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/*
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* $ scripts/lfsr.py 0x300000 4166667 16
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*
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* 33.33 ms
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*/
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localparam TIMER_RESET = 22'h27b194;
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/* 16 cycles */
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localparam TEST_TIMER_RESET = 22'h15557f;
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reg active, active_next;
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reg [LEDS - 1:0] out_next, triggered, triggered_next;
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reg [21:0] lfsr, lfsr_next;
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initial begin
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active = 0;
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triggered = {LEDS{1'b0}};
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out = {LEDS{1'b0}};
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lfsr = TEST_TIMER_RESET;
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end
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always @(*) begin
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active_next = active;
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triggered_next = triggered | triggers;
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out_next = out;
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lfsr_next = { lfsr[20:0], lfsr[21] ^ lfsr[20] };
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if (&lfsr) begin
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if (active) begin
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active_next = 0;
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triggered_next = triggered_next & ~out;
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out_next = {LEDS{1'b0}};
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end else begin
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active_next = 1;
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out_next = triggered;
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end
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lfsr_next = test_mode ? TEST_TIMER_RESET : TIMER_RESET;
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end
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end
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always @(posedge clk) begin
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active <= active_next;
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triggered <= triggered_next;
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out <= out_next;
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lfsr <= lfsr_next;
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end
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endmodule
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