19 lines
453 B
Verilog
19 lines
453 B
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*/
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module iverilog_dump();
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integer levels;
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reg [4096:0] vcdfile, sdffile;
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initial begin
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if ($value$plusargs("vcd=%s", vcdfile) &&
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$value$plusargs("levels=%d", levels)) begin
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$dumpfile(vcdfile);
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$dumpvars(levels, `TOP);
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end
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if ($value$plusargs("sdf=%s", sdffile))
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$sdf_annotate(sdffile, `TOP);
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end
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endmodule
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