180 lines
4.7 KiB
Verilog
180 lines
4.7 KiB
Verilog
// SPDX-License-Identifier: AGPL-3.0-Only OR CERN-OHL-S-2.0
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/*
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* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
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*
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* This module implements a "replay buffer" for an AXI stream, allowing the
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* first BUF_SIZE cycles of a packet to be replayed. This may be done by
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* asserting replay while replayable is true.
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*
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* replayable will remain true until BUF_SIZE + 1 handshakes have occured
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* without a replay. In particular, it is possible to restart a packet
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* even after a handshake with m_axis_last set. To support this late replay
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* feature, done must be asserted when the consumer does not wish to perform
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* any more replays.
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*
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* In general, this buffer will add two cycles of latency. Additionally, there
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* will may some latency when replayable goes low. This is because the slave
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* interface stalls to avoid overwriting the first part of the packet. However,
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* it will still read ahead to the physical end of the buffer. This will result
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* in no stall as long as BUF_SIZE is at least three less than a power of two.
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*
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* Only axis_data is provided. For user, keep, etc. concatenate them into
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* axis_data.
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*/
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`include "common.vh"
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module axis_replay_buffer (
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input clk, rst,
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/* AXI Stream slave */
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input [DATA_WIDTH - 1:0] s_axis_data,
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input s_axis_valid,
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output reg s_axis_ready,
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input s_axis_last,
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/* AXI Stream master */
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output reg [DATA_WIDTH - 1:0] m_axis_data,
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output reg m_axis_valid,
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input m_axis_ready,
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output reg m_axis_last,
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/* Control */
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/*
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* Replay the packet. May be asserted any time replayable is high,
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* including after BUF_SIZE handshakes have occured and after
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* m_axis_last is high. Must not be asserted when replayable is low.
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*/
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input replay,
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/*
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* Force replayable low. This must be asserted for packets <= BUF_SIZE,
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* since they may still be replayed even after the end of the packet.
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*/
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input done,
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/*
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* High when replay may be asserted.
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*/
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output reg replayable
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);
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parameter DATA_WIDTH = 9;
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parameter BUF_SIZE = 54;
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localparam BUF_WIDTH = $clog2(BUF_SIZE + 1);
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reg s_axis_ready_next;
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reg m_axis_valid_next, m_axis_last_next;
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reg sent_last, sent_last_next;
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reg [DATA_WIDTH - 1:0] buffer [(2 ** BUF_WIDTH) - 1:0];
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reg [BUF_WIDTH:0] m_ptr, m_ptr_next, s_ptr, s_ptr_next, last_ptr,
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last_ptr_next, max_s_ptr;
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reg last, last_next;
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reg full, full_next, empty, replayable_next, we, re;
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always @(*) begin
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we = 0;
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s_ptr_next = s_ptr;
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last_next = last;
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last_ptr_next = last_ptr;
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if (s_axis_valid && s_axis_ready) begin
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we = 1;
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s_ptr_next = s_ptr + 1;
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if (s_axis_last) begin
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last_next = 1;
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last_ptr_next = s_ptr;
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end
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end
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empty = s_ptr == m_ptr;
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max_s_ptr = { ~m_ptr[BUF_WIDTH], m_ptr[BUF_WIDTH - 1:0] };
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full = s_ptr == max_s_ptr;
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/* Value of full assuming no movement on the master interface */
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full_next = s_ptr_next == max_s_ptr;
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if (replayable)
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s_axis_ready_next = &s_ptr[BUF_WIDTH - 1:0] == s_ptr[BUF_WIDTH];
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else
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s_axis_ready_next = !full_next;
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if (last_next)
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s_axis_ready_next = 0;
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/* read the next datum (if it's available)... */
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m_axis_valid_next = !empty;
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m_axis_last_next = last && m_ptr == last_ptr;
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re = !empty;
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m_ptr_next = m_ptr + !empty;
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/* ...except if we need to stall */
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if (m_axis_valid && !m_axis_ready) begin
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m_axis_valid_next = m_axis_valid;
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m_axis_last_next = m_axis_last;
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re = 0;
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m_ptr_next = m_ptr;
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end
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replayable_next = replayable;
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sent_last_next = sent_last;
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if (m_axis_valid && m_axis_ready) begin
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replayable_next = replayable && (replay || m_ptr != BUF_SIZE + 1);
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sent_last_next = sent_last || m_axis_last;
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end
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if (done)
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replayable_next = 0;
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if (sent_last && !replayable) begin
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m_ptr_next = 0;
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s_ptr_next = 0;
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last_next = 0;
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replayable_next = 1;
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sent_last_next = 0;
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end
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if (replay) begin
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m_ptr_next = 0;
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sent_last_next = 0;
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m_axis_valid_next = 0;
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m_axis_last_next = 0;
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end
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end
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always @(posedge clk) begin
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if (we)
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buffer[s_ptr[BUF_WIDTH - 1:0]] <= { s_axis_data };
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if (re)
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{ m_axis_data } <= buffer[m_ptr[BUF_WIDTH - 1:0]];
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last_ptr <= last_ptr_next;
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end
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always @(posedge clk, posedge rst) begin
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if (rst) begin
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m_ptr <= 0;
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s_ptr <= 0;
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last <= 0;
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replayable <= 1;
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s_axis_ready <= 0;
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m_axis_valid <= 0;
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m_axis_last <= 0;
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sent_last <= 0;
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end else begin
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m_ptr <= m_ptr_next;
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s_ptr <= s_ptr_next;
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last <= last_next;
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replayable <= replayable_next;
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s_axis_ready <= s_axis_ready_next;
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m_axis_last <= m_axis_last_next;
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m_axis_valid <= m_axis_valid_next;
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sent_last <= sent_last_next;
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end
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end
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`ifndef SYNTHESIS
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/* This is the only way to look into a buffer... */
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genvar i;
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generate for (i = 0; i < 2 ** BUF_WIDTH; i = i + 1)
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wire [DATA_WIDTH - 1:0] tmp = buffer[i];
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endgenerate
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`endif
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endmodule
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