57 lines
2.5 KiB
Plaintext
57 lines
2.5 KiB
Plaintext
= Interfaces
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Throughout this project, a variety of interfaces, some standard and some
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bespoke, are used to communicate between cores.
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== "`MII`"
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This is the Media-Independent Interface (MII) described by IEEE 802.3 clause 22.
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However, instead of RX and TX clocks, clock-enables are used instead. This is a
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better fit for the clocking resources found on iCE40 FPGAs. In the 125 MHz clock
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domain used by these cores, the clock enable is asserted every 5 clock cycles.
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The clock enable generated by `pcs_rx` may vary somewhat from this due to
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differences in the local and far end clocks. The `mii_elastic_buffer` module can
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be used to smooth out these variations over the course of a frame.
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== "`100Base-X`"
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This is a bespoke interface used by modules in the receive data path below the
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PCS layer. It consists of three signals: `clk`, `data`, and `data_valid`. `data`
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and `data_valid` are both two bits wide. Data is transferred on the rising edge
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of `clk`. The following table shows the relation between `data` and
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`data_valid`:
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[cols="1,1,1"]
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|===
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| `data_valid` | `data[1]` | `data[0]`
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| 0 | Invalid | Invalid
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| 1 | Valid | Invalid
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| 2 or 3 | Valid | Valid
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|===
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In the case where both bits in `data` are valid, `data[1]` is the most recent
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bit. As a consequence, when `data_valid` is non-zero, `data[1]` always holds the
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new bit to process. Because three bits cannot be transferred at once, only
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`data_valid[1]` is necessary to determine if two bits are to be transferred.
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However, all cores which generate `data_valid` must not generate a value of 3
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for `data_valid`.
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== AXI-Stream
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This is https://zipcpu.com/doc/axi-stream.pdf[AMBA 4 AXI4-Stream], minus several
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signals. Generally, `ARESETn`, `TSTRB`, `TKEEP`, `TID`, `TDEST` are omitted.
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Sometimes `TUSER` is omitted as well. Additionally, the `A` and `T` prefixes
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are not used. When the `user` signal is present, it generally indicates that the
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associated data is erronious.
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== Wishbone
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This is https://cdn.opencores.org/downloads/wbspec_b4.pdf[Wishbone B4] in
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non-pipelined ("`classic`") mode. This imposes a performance penalty on the bus,
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but wishbone is just used for management registers so I am not too concerned.
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Generally, `RST`, `TGA`, `TGC`, `TGD`, `RTY`, `SEL`, and `LOCK` signals are
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omitted. The `_I` and `_O` suffixes are not used. `DAT` is named `data_read` or
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`data_write`, depending on the direction of transfer. `ADR` is expanded to
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`addr`. All cores have 16-bit ports with 16-bit granularity.
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