The AGPL was mostly a placeholder until I determined a better license to
use. TBH I wasn't expecting that anyone would find this repo.
Closes: #1
Signed-off-by: Sean Anderson <seanga2@gmail.com>
While manually dumping signals with a macro works OK for standalone
modules, it doesn't work when multiple modules are included. Instead,
create a second top-level module to dump signals. Inspired (once again)
by [1].
[1] https://github.com/steveicarus/iverilog/issues/376#issuecomment-709907692
Signed-off-by: Sean Anderson <seanga2@gmail.com>
As it turns out,
reg foo = 0;
is not the same as
reg foo; initial foo = 0;
but instead is equivalent to
reg foo; always @(*) foo = 0;
This is rather silly. Convert all existing (lucky) examples to the
second form.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The specification requires that the MII be isolated before the STA
clears the BMCR.ISOLATE bit. Add support for this to the MII I/O
modules.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
The actitecture is overall fairly similar to the receive interface,
except that the directions are mostly different. The timing is a bit
easier, since we control the ce signal. Data is sampled one clock before
tx_clk goes high, which is the earliest that it is guarantee'd to be
valid. We could get an extra half-clock by having tx_clk go high at the
negedge of clk, but it's unnecessary at the moment.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson