Expand a bit on the AXI stream and Wishbone interfaces, documenting the
particular choices we use. The reset signalling could likely also use
some further documentation, but I have deferred that until I have gone
though all the cores and fixed bugs.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds the core of the UART-Wishbone bridge. The protocol has
a variable-length address phase to help reduce overhead. Multiple
in-flight commands are not supported, although this could be resolved
with some FIFOs.
Signed-off-by: Sean Anderson <seanga2@gmail.com>