skywater
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ethernet
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3 Commits

Author SHA1 Message Date
Sean Anderson a549fca957 Add UART receive module 
Add the recieve half of the UART. It's more or less the inverse of the
transmit half, except we manage the state explicitly. I originally did
this in hopes that yosys would recode the FSM, but it doesn't like the
subtraction in the D* states. I left in the async reset anyway since it
reduces the LUT count.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2023-02-28 23:50:36 -05:00
Sean Anderson e44d381c20 Add UART transmit module 
I join everyone and their mother in creating my own UART. 8n1 only, and 2
baud rates. Accepts AXI-stream.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2023-02-28 22:26:05 -05:00
Sean Anderson e27d79b7c1 Add a README 
It is high time to add some documentation.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2023-02-20 23:34:10 -05:00