Commit Graph

1 Commits

Author SHA1 Message Date
Sean Anderson 52bc62814e Add wishbone register
This module registers all signals on a wishbone bus. This increases
latency/decreases throughput, but the wishbone cores here are just for
management, so that's not really critical.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2023-03-06 22:00:41 -05:00