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ethernet
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3 Commits

Author SHA1 Message Date
Sean Anderson 067029ad3b uart_rx: Fix incorrect handshaking 
AXI stream is transferred exactly on the rising edge of the clock. Use
the current value of the signals for this, instead of past values.
Simulate a slower slave to ensure this is tested.

Fixes: a549fca ("Add UART receive module")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2023-03-04 16:43:22 -05:00
Sean Anderson 587a567188 tb: uart_rx: Export putchar 
This function is useful for other testbenches. Export it.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2023-03-04 14:29:31 -05:00
Sean Anderson a549fca957 Add UART receive module 
Add the recieve half of the UART. It's more or less the inverse of the
transmit half, except we manage the state explicitly. I originally did
this in hopes that yosys would recode the FSM, but it doesn't like the
subtraction in the D* states. I left in the async reset anyway since it
reduces the LUT count.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
 2023-02-28 23:50:36 -05:00