The AGPL was mostly a placeholder until I determined a better license to
use. TBH I wasn't expecting that anyone would find this repo.
Closes: #1
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Document how the LFSR initial values are generated. Also fix several
off-by-one errors (where the documented cycles was not quite right).
Signed-off-by: Sean Anderson <seanga2@gmail.com>
AXI stream is transferred exactly on the rising edge of the clock. Use
the current value of the signals for this, instead of past values.
Simulate a slower slave to ensure this is tested.
Fixes: a549fca ("Add UART receive module")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add the recieve half of the UART. It's more or less the inverse of the
transmit half, except we manage the state explicitly. I originally did
this in hopes that yosys would recode the FSM, but it doesn't like the
subtraction in the D* states. I left in the async reset anyway since it
reduces the LUT count.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson