The AGPL was mostly a placeholder until I determined a better license to
use. TBH I wasn't expecting that anyone would find this repo.
Closes: #1
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Add an option to register the wishbone busses post-mux. This can help
achieve timing, since the phys are often in different parts of the FPGA.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
If the input and output clock enables are exactly aligned, the elastic
buffer can overflow (as it waits for 2 entries before offering, and
there's a cycle of latency). Increase the size so we don't run into that
situation.
Fixes: b351beb ("Add hub")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
It's convenient to be able to adjust this parameter if the counters ever
end up on the critical path. Support adjusting it from hub.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This adds a basic hub wrapper module which incorperates the core
introduced in b68e131 ("Add a basic hub"). For each port, it
instantiates a phy (itself using a phy_internal wrapper) and an elastic
buffer. A WISHBONE parameter is used to control whether to instantiate a
wishbone interface. When disabled, we just respond to any request with
err. I've ommitted a separate testbench for phy_internal, since it is
much easier to create a smoke test using the hub interface.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson