Store synthesis logs

Yosys is very verbose, so I usually run it quietly. However, it may be
usefult to review synthesis logs when debugging.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

Makefile

@@ -7,14 +7,19 @@ PNR = nextpnr-ice40
 ICARUS = iverilog
 VVP = vvp
 
+.DELETE_ON_ERROR:
+
 .PHONY: all
 all: rtl/pcs.asc
 
 .PHONY: FORCE
 FORCE:
 
-%.synth.json: %.v
-	$(SYNTH) -q -E $@.d -p "synth_ice40 -top $(*F)" -b json -o $@ -f verilog $<
+log:
+	mkdir $@
+
+%.synth.json: %.v | log
+	$(SYNTH) -q -E $@.d -p "synth_ice40 -top $(*F)" -b json -o $@ -f verilog $< -l log/$(*F).synth
 
 define run-jsontov =
 	( echo '`include "common.vh"'; grep timescale $*.v; \

rtl/pcs.v

@@ -637,62 +637,3 @@ end
 `endif
 
 endmodule
-
-/* For timing purposes */
-module top (
-	input clk, in_next,
-	output out
-);
-
-	reg [11:0] in;
-	always @(posedge clk)
-		in <= { in[10:0], in_next };
-
-	wire tx_ce;
-	wire tx_en;
-	wire [3:0] txd;
-	wire tx_er;
-	wire [1:0] pma_data_rx;
-	wire [1:0] pma_data_rx_valid;
-	wire link_status;
-
-	assign { tx_ce, tx_en, txd, tx_er, pma_data_rx, pma_data_rx_valid, link_status } = in;
-
-	wire rx_ce;
-	wire rx_dv;
-	wire [3:0] rxd;
-	wire rx_er;
-	wire pma_data_tx;
-	wire crs;
-	wire col;
-
-	reg [9:0] out_next;
-
-	always @(posedge clk)
-		out_next <= { rx_ce, rx_dv, rxd, rx_er, pma_data_tx, crs, col };
-
-	assign out = ^out_next;
-
-	pcs pcs (
-		clk,
-		tx_ce,
-		tx_en,
-		txd,
-		tx_er,
-
-		clk,
-		rx_ce,
-		rx_dv,
-		rxd,
-		rx_er,
-
-		crs,
-		col,
-
-		pma_data_tx,
-		pma_data_rx,
-		pma_data_rx_valid,
-		link_status
-	);
-
-endmodule