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ethernet
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Store synthesis logs 

Yosys is very verbose, so I usually run it quietly. However, it may be
usefult to review synthesis logs when debugging.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2022-10-16 18:00:02 -04:00
parent 6af697b4eb
commit b060eef25e
2 changed files with 7 additions and 61 deletions
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9
Makefile
View File

@ -7,14 +7,19 @@ PNR = nextpnr-ice40
ICARUS = iverilog ICARUS = iverilog
VVP = vvp VVP = vvp
.DELETE_ON_ERROR:
.PHONY: all .PHONY: all
all: rtl/pcs.asc all: rtl/pcs.asc
.PHONY: FORCE .PHONY: FORCE
FORCE: FORCE:
%.synth.json: %.v log:
$(SYNTH) -q -E $@.d -p "synth_ice40 -top $(*F)" -b json -o $@ -f verilog $< mkdir $@
%.synth.json: %.v | log
$(SYNTH) -q -E $@.d -p "synth_ice40 -top $(*F)" -b json -o $@ -f verilog $< -l log/$(*F).synth
define run-jsontov = define run-jsontov =
( echo '`include "common.vh"'; grep timescale $*.v; \ ( echo '`include "common.vh"'; grep timescale $*.v; \

59
rtl/pcs.v
View File

@ -637,62 +637,3 @@ end
`endif `endif
endmodule endmodule
/* For timing purposes */
module top (
input clk, in_next,
output out
);
reg [11:0] in;
always @(posedge clk)
in <= { in[10:0], in_next };
wire tx_ce;
wire tx_en;
wire [3:0] txd;
wire tx_er;
wire [1:0] pma_data_rx;
wire [1:0] pma_data_rx_valid;
wire link_status;
assign { tx_ce, tx_en, txd, tx_er, pma_data_rx, pma_data_rx_valid, link_status } = in;
wire rx_ce;
wire rx_dv;
wire [3:0] rxd;
wire rx_er;
wire pma_data_tx;
wire crs;
wire col;
reg [9:0] out_next;
always @(posedge clk)
out_next <= { rx_ce, rx_dv, rxd, rx_er, pma_data_tx, crs, col };
assign out = ^out_next;
pcs pcs (
clk,
tx_ce,
tx_en,
txd,
tx_er,
clk,
rx_ce,
rx_dv,
rxd,
rx_er,
crs,
col,
pma_data_tx,
pma_data_rx,
pma_data_rx_valid,
link_status
);
endmodule