mii_io_rx: Drive all signals in all branches
This avoids some edge cases with if statements and default values. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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@ -24,31 +24,31 @@ module mii_io_rx (
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reg rx_clk_p_next, rx_clk_n, rx_clk_n_next;
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reg rx_clk_p_next, rx_clk_n, rx_clk_n_next;
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reg [1:0] state = HIGH, state_next;
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reg [1:0] state, state_next;
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initial state = HIGH;
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localparam LOW = 2;
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localparam LOW = 2;
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localparam RISING = 1;
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localparam RISING = 1;
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localparam HIGH = 0;
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localparam HIGH = 0;
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always @(*) begin
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always @(*) begin
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rx_clk_p_next = 0;
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rx_clk_n_next = 0;
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if (ce) begin
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if (ce) begin
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state_next = LOW;
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state_next = LOW;
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end else case (state)
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rx_clk_p_next = 0;
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LOW: begin
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rx_clk_n_next = 0;
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end else if (state == LOW) begin
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state_next = RISING;
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state_next = RISING;
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end
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rx_clk_p_next = 0;
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RISING: begin
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rx_clk_n_next = 0;
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end else if (state == RISING) begin
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state_next = HIGH;
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state_next = HIGH;
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rx_clk_p_next = 0;
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rx_clk_n_next = 1;
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rx_clk_n_next = 1;
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end
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end else begin
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HIGH: begin
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state_next = HIGH;
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state_next = HIGH;
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rx_clk_p_next = 1;
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rx_clk_p_next = 1;
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rx_clk_n_next = 1;
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rx_clk_n_next = 1;
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end
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end
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endcase
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end
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end
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always @(posedge clk) begin
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always @(posedge clk) begin
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