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pcs: Fix some lint 

There were two unused variables; remove them. The wrong type of
assignments were used; fix them.

Fixes: d351291 ("Initial commit")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2022-08-06 15:21:15 -04:00
parent d2b4f9b061
commit 93e91e3eb0
1 changed files with 2 additions and 4 deletions
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6
rtl/pcs.v
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@ -450,8 +450,6 @@ module pcs_rx (
reg ce_next, valid_next, err_next; reg ce_next, valid_next, err_next;
reg [2:0] state, state_next; reg [2:0] state, state_next;
initial state = IDLE; initial state = IDLE;
/* Receive shift buffer */
reg [9:0] buffer, buffer_next;
/* Whether we are aligned and receiving */ /* Whether we are aligned and receiving */
reg rx_next; reg rx_next;
@ -645,7 +643,7 @@ module top (
reg [11:0] in; reg [11:0] in;
always @(posedge clk) always @(posedge clk)
in = { in[10:0], in_next }; in <= { in[10:0], in_next };
wire tx_ce; wire tx_ce;
wire tx_en; wire tx_en;
@ -668,7 +666,7 @@ module top (
reg [9:0] out_next; reg [9:0] out_next;
always @(posedge clk) always @(posedge clk)
out_next = { rx_ce, rx_dv, rxd, rx_er, pma_data_tx, crs, col }; out_next <= { rx_ce, rx_dv, rxd, rx_er, pma_data_tx, crs, col };
assign out = ^out_next; assign out = ^out_next;