rtl: Document calculation of LFSRs

Document how the LFSR initial values are generated. Also fix several
off-by-one errors (where the documented cycles was not quite right).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2023-03-15 13:44:20 -04:00
parent c5df9ff5d5
commit 8887f774d0
5 changed files with 30 additions and 20 deletions

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@ -38,21 +38,19 @@ module descramble (
* We use a LFSR for the unlock counter in order to relax the timing * We use a LFSR for the unlock counter in order to relax the timing
* requirements. Although we could use a 16-bit register, we use * requirements. Although we could use a 16-bit register, we use
* a 17-bit one to reduce the number of taps we need. Values were * a 17-bit one to reduce the number of taps we need. Values were
* generated with the following python script: * generated with:
* *
* lfsr = 0x1ffff * $ scripts/lfsr.py 0x12000 90460 45125 625
* for _ in range(2**17 - cycles - 1):
* lfsr = ((lfsr << 1) & 0x1ffff) | (((lfsr >> 16) & 1) ^ ((lfsr >> 13) & 1))
* *
* The amount of time without recieving consecutive idles before we * The amount of time without receiving consecutive idles before we
* unlock. This must be greater than 361us (7.2.3.3(f)), which is * unlock. This must be greater than 361us (7.2.3.3(f)), which is
* 45125 cycles at 125MHz. * 45125 cycles at 125MHz.
*/ */
localparam UNLOCK_VALUE = 17'h29fc; localparam UNLOCK_VALUE = 17'h05b08;
/* One 9000-byte jumbo frame plus an extra preamble */ /* One 9000-byte jumbo frame plus an extra preamble */
localparam JUMBO_UNLOCK_VALUE = 17'h12d84; localparam JUMBO_UNLOCK_VALUE = 17'h053f9;
/* One minimum-length packet plus some extra (5us or 625 cycles) */ /* One minimum-length packet plus some extra (5us or 625 cycles) */
localparam TEST_UNLOCK_VALUE = 17'h11077; localparam TEST_UNLOCK_VALUE = 17'h020ef;
reg [16:0] unlock_counter, unlock_counter_next; reg [16:0] unlock_counter, unlock_counter_next;
always @(*) begin always @(*) begin

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@ -21,9 +21,14 @@ module led_blinker (
parameter LEDS = 2; parameter LEDS = 2;
/*
* $ scripts/lfsr.py 0x140000 0x1fffff 16
*
* 16.78 ms
*/
localparam TIMER_RESET = 21'h1ffffe; localparam TIMER_RESET = 21'h1ffffe;
/* 16 cycles before the end */ /* 16 cycles */
localparam TEST_TIMER_RESET = 21'h0ccccf; localparam TEST_TIMER_RESET = 21'h13333f;
reg active, active_next; reg active, active_next;
reg [LEDS - 1:0] out_next, triggered, triggered_next; reg [LEDS - 1:0] out_next, triggered, triggered_next;
@ -50,7 +55,7 @@ module led_blinker (
active_next = 1; active_next = 1;
out_next = triggered; out_next = triggered;
end end
lfsr_next = test_mode ? 21'hCCCCF : 21'h1FFFFE; lfsr_next = test_mode ? TEST_TIMER_RESET : TIMER_RESET;
end end
end end

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@ -88,14 +88,13 @@ module phy_core (
); );
/* /*
* LFSR counter; see descramble.v for details on how these values were * $ scripts/lfsr.py 0x12000 41250 16
* generated.
* *
* 50000 cycles or 400 us at 125MHz * 41250 cycles or 330 us at 125MHz
*/ */
localparam STABILIZE_VALUE = 17'h1ac86; localparam STABILIZE_VALUE = 17'h1590c;
/* 16 cycles; there's no instability while testing */ /* 16 cycles; there's no instability while testing */
localparam TEST_STABILIZE_VALUE = 17'h11c71; localparam TEST_STABILIZE_VALUE = 17'h038e3;
reg link_status_next; reg link_status_next;
initial link_status = 0; initial link_status = 0;

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@ -25,10 +25,14 @@ module uart_rx (
output reg frame_error output reg frame_error
); );
/* 1085 cycles, for 115200 baud with a 125 MHz clock */ /*
* $ scripts/lfsr.py 0x500 1085 543 31 16
*
* 115200 baud with a 125 MHz clock
*/
parameter SLOW_FULL = 11'h78c; parameter SLOW_FULL = 11'h78c;
parameter SLOW_HALF = 11'h202; parameter SLOW_HALF = 11'h202;
/* 31 cycles, for 4M baud with a 125 MHz clock */ /* 4M baud with a 125 MHz clock */
parameter FAST_FULL = 11'h68e; parameter FAST_FULL = 11'h68e;
parameter FAST_HALF = 11'h34c; parameter FAST_HALF = 11'h34c;

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@ -20,9 +20,13 @@ module uart_tx (
input high_speed input high_speed
); );
/* 1085 cycles, for 115200 baud with a 125 MHz clock */ /*
* $ scripts/lfsr.py 0x500 1085 31
*
* 115200 baud with a 125 MHz clock
*/
parameter SLOW_VALUE = 11'h78c; parameter SLOW_VALUE = 11'h78c;
/* 31 cycles, for 4M baud with a 125 MHz clock */ /* 4M baud with a 125 MHz clock */
parameter FAST_VALUE = 11'h68e; parameter FAST_VALUE = 11'h68e;
reg ready_next; reg ready_next;