tb: mdio_regs: Export wb_xfer

Convert xfer into a form which can be reused in other testbenches.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2023-02-20 16:54:18 -05:00
parent fc3cce02ea
commit 83d805bb79
1 changed files with 30 additions and 18 deletions

View File

@ -37,6 +37,25 @@ BMSR_EXTCAP = BIT(0)
VCR_DTEST = BIT(15) VCR_DTEST = BIT(15)
VCR_LTEST = BIT(14) VCR_LTEST = BIT(14)
async def wb_xfer(signals, addr, data=None):
await FallingEdge(signals['clk'])
signals['stb'].value = 1
signals['addr'].value = addr
if data is None:
signals['we'].value = 0
else:
signals['we'].value = 1
signals['data_write'].value = data
await FallingEdge(signals['clk'])
assert signals['ack'].value or signals['err'].value
signals['stb'].value = 0
signals['we'].value = LogicArray('X')
signals['addr'].value = LogicArray('X' * 4)
signals['data_write'].value = LogicArray('X' * 16)
if data is None and signals['ack'].value:
return signals['data_read'].value
@cocotb.test(timeout_time=1, timeout_unit='us') @cocotb.test(timeout_time=1, timeout_unit='us')
async def test_mdio(regs): async def test_mdio(regs):
regs.cyc.value = 1 regs.cyc.value = 1
@ -49,24 +68,17 @@ async def test_mdio(regs):
await Timer(1) await Timer(1)
await cocotb.start(Clock(regs.clk, 8, units='ns').start()) await cocotb.start(Clock(regs.clk, 8, units='ns').start())
async def xfer(regad, data=None): def xfer(regad, data=None):
await FallingEdge(regs.clk) return wb_xfer({
regs.stb.value = 1 'clk': regs.clk,
regs.addr.value = regad 'stb': regs.stb,
if data is None: 'we': regs.we,
regs.we.value = 0 'addr': regs.addr,
else: 'data_write': regs.data_write,
regs.we.value = 1 'data_read': regs.data_read,
regs.data_write.value = data 'ack': regs.ack,
'err': regs.err,
await FallingEdge(regs.clk) }, regad, data)
assert regs.ack.value or regs.err.value
regs.stb.value = 0
regs.we.value = LogicArray('X')
regs.addr.value = LogicArray('X' * 4)
regs.data_write.value = LogicArray('X' * 16)
if data is None and regs.ack.value:
return regs.data_read.value
async def reg_toggle(reg, bit, signal, ro_mask=0): async def reg_toggle(reg, bit, signal, ro_mask=0):
if signal: if signal: