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mdio_regs: Test OUI mapping to PHYID 

The OUI in the PHY ID is "bit-reversed," AKA each byte is bit reversed,
but the overall order is the same. This is a bit more complex than I
initially thought. Fix the mapping, and use a non-zero OUI for testing.

Fixes: d9602b6 ("Add MII management functions")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2023-03-15 14:11:56 -04:00
parent 508b090983
commit 7d93f91dd3
2 changed files with 15 additions and 7 deletions
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18
rtl/mdio_regs.v
View File

@ -28,8 +28,11 @@ module mdio_regs (
output reg link_monitor_test
);
/* The current price of a CID is $805... */
parameter [23:0] OUI = 0;
/*
* A test OUI in "canonical" form. Don't use this! It's just here to
* test the bit-reversal logic (as seen in 802 8.2.2).
*/
parameter [23:0] OUI = 24'hacde48;
parameter [5:0] MODEL = 0;
parameter [3:0] REVISION = 0;
/*
@ -199,14 +202,19 @@ module mdio_regs (
link_status_latched_next = link_status;
end
ID1: begin
for (i = 0; i < 16; i = i + 1)
data_read_next[i] = OUI[17 - i];
/* "bit-reverse" the OUI */
for (i = 6; i < 8; i = i + 1)
data_read_next[i - 6] = OUI[7 - i];
for (i = 0; i < 8; i = i + 1)
data_read_next[i + 2] = OUI[15 - i];
for (i = 0; i < 6; i = i + 1)
data_read_next[i + 10] = OUI[23 - i];
end
ID2: begin
data_read_next[3:0] = REVISION;
data_read_next[9:4] = MODEL;
for (i = 0; i < 6; i = i + 1)
data_read_next[i + 4] = OUI[23 - i];
data_read_next[i + 10] = OUI[7 - i];
end
NWCR: if (ENABLE_COUNTERS) begin
data_read_next = nwc;

4
tb/mdio_regs.py
View File

@ -116,10 +116,10 @@ async def test_mdio(regs):
assert await xfer(BMSR) & BMSR_LSTATUS
await xfer(PHYID1, 0xffff)
assert await xfer(PHYID1) == 0
assert await xfer(PHYID1) == 0xd5ec
await xfer(PHYID2, 0xffff)
assert await xfer(PHYID2) == 0
assert await xfer(PHYID2) == 0x4800
# I'm pretty sure this register will never be implemented
assert await xfer(EXTSTATUS) is None