tb: axis_mii_tx: Simulate a longer reset
Simulate a reset lasting for at least once clock cycle to ensure our external interfaces act sane. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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@ -29,10 +29,13 @@ async def init(mac):
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mac.axis_err.value = 0
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mac.axis_err.value = 0
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mac.short_backoff.value = 1
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mac.short_backoff.value = 1
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mac.half_duplex.value = 1
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mac.half_duplex.value = 1
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await Timer(1)
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mac.rst.value = 0
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async def _init():
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await cocotb.start(Clock(mac.clk, 8, units='ns').start())
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await Timer(1)
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await FallingEdge(mac.clk)
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await cocotb.start(Clock(mac.clk, 8, units='ns').start())
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await FallingEdge(mac.clk)
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mac.rst.value = 0
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await cocotb.start(_init())
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def send_packet(mac, packet, **kwargs):
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def send_packet(mac, packet, **kwargs):
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return axis_replay_buffer.send_packet({
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return axis_replay_buffer.send_packet({
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@ -119,11 +122,11 @@ async def get_status(mac):
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underflow = 0
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underflow = 0
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while not (ok or gave_up or late or underflow) or mac.mii_tx_en.value:
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while not (ok or gave_up or late or underflow) or mac.mii_tx_en.value:
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await RisingEdge(mac.clk)
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ok += mac.transmit_ok.value
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ok += mac.transmit_ok.value
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gave_up += mac.gave_up.value
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gave_up += mac.gave_up.value
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late += mac.late_collision.value
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late += mac.late_collision.value
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underflow += mac.underflow.value
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underflow += mac.underflow.value
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await FallingEdge(mac.clk)
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assert ok + gave_up + late + underflow == 1
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assert ok + gave_up + late + underflow == 1
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if ok:
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if ok:
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@ -202,7 +205,7 @@ async def test_send(mac, ratio):
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await RisingEdge(mac.clk)
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await RisingEdge(mac.clk)
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# The first IPG may not be exact
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# The first IPG may not be exact
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if i:
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if i:
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assert get_sim_time('step') - start == get_sim_steps(12 * 80 - 4, 'ns')
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assert get_sim_time('step') - start == get_sim_steps(12 * 80, 'ns')
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compare(await recv.join(), packet)
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compare(await recv.join(), packet)
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assert await status.join() == Status.OK
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assert await status.join() == Status.OK
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