axis_mii_tx: Delay error handling by one cycle
The 2 ns delay when reading from a BRAM makes it hard to close timing, since buf_err affects the state machine. Address this by not acting on errors for a clock cycle. We will output bad data for a cycle, but we are going to corrupt the FCS anyway so it doesn't matter. We also have to check for errors in the PAD/FCS states, to ensure they don't slip past. Signed-off-by: Sean Anderson <seanga2@gmail.com>
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@ -182,7 +182,7 @@ module axis_mii_tx (
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reg [5:0] state_counter, state_counter_next;
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reg [5:0] state_counter, state_counter_next;
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reg [9:0] lfsr, lfsr_next, backoff, backoff_next;
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reg [9:0] lfsr, lfsr_next, backoff, backoff_next;
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reg transmit_ok_next, gave_up_next, late_collision_next;
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reg transmit_ok_next, gave_up_next, late_collision_next;
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reg underflow_next;
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reg underflow_next, err, err_next;
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always @(*) begin
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always @(*) begin
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mii_tx_ce_next_next_next = 0;
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mii_tx_ce_next_next_next = 0;
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@ -223,6 +223,10 @@ module axis_mii_tx (
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state_counter_next = state_counter - 1;
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state_counter_next = state_counter - 1;
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end
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end
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err_next = 0;
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if (buf_ready && buf_valid && buf_err)
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err_next = 1;
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transmit_ok_next = 0;
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transmit_ok_next = 0;
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gave_up_next = 0;
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gave_up_next = 0;
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late_collision_next = 0;
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late_collision_next = 0;
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@ -319,18 +323,13 @@ module axis_mii_tx (
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end
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end
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endcase
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endcase
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if (!buf_valid || buf_err) begin
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if (!buf_valid) begin
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if (buf_valid && buf_last)
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if (buf_last)
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state_next = JAM_FAIL;
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state_next = JAM_FAIL;
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else
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else
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state_next = JAM_DRAIN;
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state_next = JAM_DRAIN;
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/*
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state_counter_next = JAM_BYTES - 1;
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* Start jamming immediately to avoid
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* sending Xs
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*/
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state_counter_next = JAM_BYTES - 2;
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data_next = DATA_JAM;
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underflow_next = 1;
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underflow_next = 1;
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if (state == DATA_EARLY)
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if (state == DATA_EARLY)
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done_next = 1;
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done_next = 1;
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@ -351,6 +350,14 @@ module axis_mii_tx (
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state_counter_next = JAM_BYTES - 1;
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state_counter_next = JAM_BYTES - 1;
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end
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end
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end
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end
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if (err) begin
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state_next = JAM_DRAIN;
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state_counter_next = JAM_BYTES - 1;
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underflow_next = 1;
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if (state == DATA_EARLY)
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done_next = 1;
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end
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end
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end
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PAD_EARLY,
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PAD_EARLY,
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PAD_LATE: begin
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PAD_LATE: begin
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@ -378,6 +385,14 @@ module axis_mii_tx (
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end
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end
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end
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end
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end
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end
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if (err) begin
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state_next = JAM_FAIL;
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state_counter_next = JAM_BYTES - 1;
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underflow_next = 1;
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if (state == PAD_EARLY)
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done_next = 1;
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end
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end
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end
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FCS: begin
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FCS: begin
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if (do_state) begin
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if (do_state) begin
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@ -398,6 +413,12 @@ module axis_mii_tx (
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transmit_ok_next = 0;
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transmit_ok_next = 0;
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end
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end
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end
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end
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if (err) begin
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state_next = JAM_FAIL;
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state_counter_next = JAM_BYTES - 1;
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underflow_next = 1;
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end
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end
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end
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IPG_OR_JAM: begin
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IPG_OR_JAM: begin
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if (do_state) begin
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if (do_state) begin
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@ -499,6 +520,7 @@ module axis_mii_tx (
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late_collision <= 0;
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late_collision <= 0;
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underflow <= 0;
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underflow <= 0;
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buf_ready <= 0;
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buf_ready <= 0;
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err <= 0;
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done <= 0;
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done <= 0;
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replay <= 0;
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replay <= 0;
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end else begin
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end else begin
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@ -513,6 +535,7 @@ module axis_mii_tx (
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state <= state_next;
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state <= state_next;
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state_counter <= state_counter_next;
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state_counter <= state_counter_next;
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buf_ready <= buf_ready_next;
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buf_ready <= buf_ready_next;
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err <= err_next;
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data <= data_next;
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data <= data_next;
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replay <= replay_next;
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replay <= replay_next;
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done <= done_next;
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done <= done_next;
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