Add examples

This adds an example of how to integrate the hub into a design. For the
moment, wishbone is disabled, but I plan to add a uart bridge in the
future.

Signed-off-by: Sean Anderson <seanga2@gmail.com>

Makefile

@@ -10,7 +10,7 @@ VVP = vvp
 .DELETE_ON_ERROR:
 
 .PHONY: all
-all: rtl/pcs.asc
+all: examples/breakout_hub/top.bin
 
 .PHONY: FORCE
 FORCE:
@@ -152,3 +152,4 @@ clean:
 	rm -f *.fst
 	rm -rf log
 	rm -f $(addprefix rtl/*,$(CLEAN_EXT))
+	rm -f $(addprefix examples/*/*,$(CLEAN_EXT))

examples/README.adoc

@@ -0,0 +1,8 @@
+= Examples
+
+This directory contains example designs showcasing different ways to use the
+cores in this project.
+
+:leveloffset: +1
+
+include::breakout_hub/README.adoc[]

examples/breakout_hub/README.adoc

@@ -0,0 +1,13 @@
+= Ethernet breakout board hub
+
+This directory contains an example design for a 4-port hub. It runs on an
+https://www.olimex.com/Products/FPGA/iCE40/iCE40HX8K-EVB/[Olimex iCE40HX8K-EVB]
+combined with an ethernet breakout board.
+
+To compile this design, run
+
+    $ make examples/breakout_hub/top.bin
+
+from the root directory of this repository. NextPNR can't always reliably place
+and route this design (due to heavy I/O congestion), so you may need to run
+this multiple times.

examples/breakout_hub/top.pcf

@@ -0,0 +1,34 @@
+set_frequency	clk_100	100
+set_frequency	clk_125	125
+set_frequency	clk_250	250
+set_io	clk_100			J3
+set_io	indicate_data[0]	B1
+set_io	indicate_data[1]	C2
+set_io	indicate_data[2]	D2
+set_io	indicate_data[3]	G5
+set_io	request_data[0]		E4
+set_io	request_data[1]		B2
+set_io	request_data[2]		G3
+set_io	request_data[3]		F3
+set_io	signal_detect[0]	G1
+set_io	signal_detect[1]	J5
+set_io	signal_detect[2]	H2
+set_io	signal_detect[3]	J4
+set_io	collision		M12
+set_io	transmitting		R16
+set_io	link_act[0]		H1
+set_io	link_act[1]		C1
+set_io	link_act[2]		E3
+set_io	link_act[3]		F2
+set_io	speed[0]		F5
+set_io	speed[1]		F1
+set_io	speed[2]		H5
+set_io	speed[3]		E2
+set_io	polarity[0]		G2
+set_io	polarity[1]		D1
+set_io	polarity[2]		H4
+set_io	polarity[3]		G4
+set_io	loopback[0]		J2
+set_io	loopback[1]		F4
+set_io	loopback[2]		H6
+set_io	loopback[3]		H3

examples/breakout_hub/top.v

@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: AGPL-3.0-Only
+/*
+ * Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
+ */
+
+`include "common.vh"
+
+module top (
+	input clk_100,
+
+	/* DP83223 */
+	input [3:0] indicate_data,
+	input [3:0] signal_detect,
+	output [3:0] request_data,
+
+	/* LEDs */
+	output collision, transmitting,
+	/* These match the names on the PCB which I am too lazy to change. */
+	output [3:0] link_act,
+	output [3:0] speed,
+
+	/* Unused for the moment */
+	input [3:0] polarity,
+	output [3:0] loopback
+);
+
+	wire clk_125, clk_250;
+
+	SB_PLL40_2F_CORE #(
+		.FEEDBACK_PATH("SIMPLE"),
+		.DIVR(4'd0),
+		.DIVF(7'd9),
+		.DIVQ(3'd2),
+		.FILTER_RANGE(3'd5),
+		.PLLOUT_SELECT_PORTB("GENCLK_HALF")
+	) pll (
+		.REFERENCECLK(clk_100),
+		.PLLOUTGLOBALA(clk_250),
+		.PLLOUTGLOBALB(clk_125),
+		.BYPASS(1'b0),
+		.RESETB(1'b1)
+	);
+
+	reg collision_raw, transmitting_raw;
+	reg [3:0] receiving;
+
+	hub #(
+		.WISHBONE(0),
+		.PORT_COUNT(4)
+	) hub (
+		.clk_125(clk_125),
+		.clk_250(clk_250),
+		.indicate_data(indicate_data),
+		.signal_detect(signal_detect),
+		.request_data(request_data),
+		.wb_cyc(1'b0),
+		.wb_stb(1'b0),
+		.collision(collision_raw),
+		.transmitting(transmitting_raw),
+		.link_status(speed),
+		.receiving(receiving)
+	);
+
+	led_blinker #(
+		.LEDS(6)
+	) blinker(
+		.clk(clk_125),
+		.triggers({ collision_raw, transmitting_raw, receiving}),
+		.out({ collision, transmitting, link_act}),
+		.test_mode(1'b0)
+	);
+
+	assign loopback = 4'b0;
+
+endmodule

rtl/phy_internal.v

@@ -126,7 +126,6 @@ module phy_internal (
 		assign wb_ack = 0;
 		assign wb_err = wb_cyc && wb_stb;
 		assign loopback = 0;
-		assign coltest = 0;
 		assign descrambler_test = 0;
 		assign link_monitor_test = 0;
 	end endgenerate