skywater
/
ethernet
mirror of https://github.com/Forty-Bot/ethernet.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

pmd_io: Align signal naming with other_io modules 

This aligns the signal naming with what is used by other modules (IEEE
names for external signals, and something else for internal).

Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2022-10-16 18:27:32 -04:00
parent b060eef25e
commit 2ce7dc016b
2 changed files with 31 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

52
rtl/pmd_io.v
View File

@ -19,14 +19,14 @@ module pmd_io (
input rx_clk_125, input rx_clk_125,
input signal_detect, input signal_detect,
input rx, input indicate_data,
output reg tx, output reg request_data,
/* PMD */ /* PMD */
output signal_status, output signal_status,
input pmd_data_tx, input tx_data,
output reg [1:0] pmd_data_rx, output reg [1:0] rx_data,
output reg [1:0] pmd_data_rx_valid output reg [1:0] rx_data_valid
); );
reg [1:0] rx_p, rx_n; reg [1:0] rx_p, rx_n;
@ -45,8 +45,8 @@ module pmd_io (
SB_IO #( SB_IO #(
.PIN_TYPE(`PIN_OUTPUT_NEVER | `PIN_INPUT_DDR), .PIN_TYPE(`PIN_OUTPUT_NEVER | `PIN_INPUT_DDR),
.IO_STANDARD("SB_LVDS_INPUT") .IO_STANDARD("SB_LVDS_INPUT")
) data_rx_pin ( ) rx_data_pin (
.PACKAGE_PIN(rx), .PACKAGE_PIN(indicate_data),
.INPUT_CLK(rx_clk_250), .INPUT_CLK(rx_clk_250),
.D_IN_0(rx_p[0]), .D_IN_0(rx_p[0]),
.D_IN_1(rx_n[0]) .D_IN_1(rx_n[0])
@ -56,10 +56,10 @@ module pmd_io (
sd_delay[0] <= signal_detect; sd_delay[0] <= signal_detect;
always @(posedge rx_clk_250) always @(posedge rx_clk_250)
rx_p[0] <= rx; rx_p[0] <= indicate_data;
always @(negedge rx_clk_250) always @(negedge rx_clk_250)
rx_n[0] <= rx; rx_n[0] <= indicate_data;
`endif `endif
/* /*
@ -116,7 +116,7 @@ module pmd_io (
initial state = A; initial state = A;
reg valid, valid_next; reg valid, valid_next;
initial valid = 0; initial valid = 0;
reg [1:0] pmd_data_rx_next, pmd_data_rx_valid_next; reg [1:0] rx_data_next, rx_data_valid_next;
reg [3:0] rx_r, rx_f; reg [3:0] rx_r, rx_f;
always @(*) begin always @(*) begin
@ -152,51 +152,51 @@ module pmd_io (
valid_next = 0; valid_next = 0;
end end
pmd_data_rx_next[0] = rx_d[2]; rx_data_next[0] = rx_d[2];
pmd_data_rx_valid_next = 1; rx_data_valid_next = 1;
case (state_next) case (state_next)
A: begin A: begin
pmd_data_rx_next[1] = rx_a[2]; rx_data_next[1] = rx_a[2];
if (state == D) if (state == D)
pmd_data_rx_valid_next = 0; rx_data_valid_next = 0;
end end
B: begin B: begin
pmd_data_rx_next[1] = rx_b[2]; rx_data_next[1] = rx_b[2];
end end
C: begin C: begin
pmd_data_rx_next[1] = rx_c[2]; rx_data_next[1] = rx_c[2];
end end
D: begin D: begin
pmd_data_rx_next[1] = rx_d[2]; rx_data_next[1] = rx_d[2];
if (state == A) begin if (state == A) begin
pmd_data_rx_next[1] = rx_a[2]; rx_data_next[1] = rx_a[2];
pmd_data_rx_valid_next = 2; rx_data_valid_next = 2;
end end
end end
endcase endcase
if (!valid_next) if (!valid_next)
pmd_data_rx_valid_next = 0; rx_data_valid_next = 0;
end end
always @(posedge rx_clk_125) begin always @(posedge rx_clk_125) begin
state <= state_next; state <= state_next;
valid <= valid_next; valid <= valid_next;
pmd_data_rx <= pmd_data_rx_next; rx_data <= rx_data_next;
pmd_data_rx_valid <= pmd_data_rx_valid_next; rx_data_valid <= rx_data_valid_next;
end end
`ifdef SYNTHESIS `ifdef SYNTHESIS
SB_IO #( SB_IO #(
.PIN_TYPE(`PIN_OUTPUT_ALWAYS | `PIN_OUTPUT_REGISTERED), .PIN_TYPE(`PIN_OUTPUT_ALWAYS | `PIN_OUTPUT_REGISTERED),
) data_txp_pin ( ) tx_datap_pin (
.PACKAGE_PIN(tx), .PACKAGE_PIN(request_data),
.OUTPUT_CLK(rx_clk_125), .OUTPUT_CLK(rx_clk_125),
.D_OUT_0(pmd_data_tx) .D_OUT_0(tx_data)
); );
`else `else
always @(posedge tx_clk) always @(posedge tx_clk)
tx <= pmd_data_tx; request_data <= tx_data;
`endif `endif
`ifndef SYNTHESIS `ifndef SYNTHESIS

10
tb/pmd_io.py
View File

@ -41,7 +41,7 @@ async def test_rx(pmd, delays):
await Timer(random.randrange(1, 8000), units='ps') await Timer(random.randrange(1, 8000), units='ps')
pmd.signal_detect.value = 1 pmd.signal_detect.value = 1
for i, delay in zip(ins, delays(len(ins))): for i, delay in zip(ins, delays(len(ins))):
pmd.rx.value = i pmd.indicate_data.value = i
try: try:
pmd.delay.value = delay pmd.delay.value = delay
except AttributeError: except AttributeError:
@ -55,14 +55,14 @@ async def test_rx(pmd, delays):
outs = [] outs = []
while pmd.signal_status.value: while pmd.signal_status.value:
await RisingEdge(pmd.rx_clk_125) await RisingEdge(pmd.rx_clk_125)
valid = pmd.pmd_data_rx_valid.value valid = pmd.rx_data_valid.value
if valid == 0: if valid == 0:
pass pass
elif valid == 1: elif valid == 1:
outs.append(pmd.pmd_data_rx[1].value) outs.append(pmd.rx_data[1].value)
else: else:
outs.append(pmd.pmd_data_rx[1].value) outs.append(pmd.rx_data[1].value)
outs.append(pmd.pmd_data_rx[0].value) outs.append(pmd.rx_data[0].value)
best_corr = -1 best_corr = -1
best_off = None best_off = None