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doc: Expand interfaces documentation 

Expand a bit on the AXI stream and Wishbone interfaces, documenting the
particular choices we use. The reset signalling could likely also use
some further documentation, but I have deferred that until I have gone
though all the cores and fixed bugs.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2023-03-15 15:12:17 -04:00
parent 12b98c8d46
commit 13ee4899a3
1 changed files with 12 additions and 7 deletions
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19
doc/interfaces.adoc
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@ -13,7 +13,7 @@ The clock enable generated by `pcs_rx` may vary somewhat from this due to
differences in the local and far end clocks. The `mii_elastic_buffer` module can differences in the local and far end clocks. The `mii_elastic_buffer` module can
be used to smooth out these variations over the course of a frame. be used to smooth out these variations over the course of a frame.
== "`PMD`" == "`100Base-X`"
This is a bespoke interface used by modules in the receive data path below the This is a bespoke interface used by modules in the receive data path below the
PCS layer. It consists of three signals: `clk`, `data`, and `data_valid`. `data` PCS layer. It consists of three signals: `clk`, `data`, and `data_valid`. `data`
@ -34,18 +34,23 @@ In the case where both bits in `data` are valid, `data[1]` is the most recent
bit. As a consequence, when `data_valid` is non-zero, `data[1]` always holds the bit. As a consequence, when `data_valid` is non-zero, `data[1]` always holds the
new bit to process. Because three bits cannot be transferred at once, only new bit to process. Because three bits cannot be transferred at once, only
`data_valid[1]` is necessary to determine if two bits are to be transferred. `data_valid[1]` is necessary to determine if two bits are to be transferred.
However, all cores which generate `data_valid` must not generate a value of 3
for `data_valid`.
== AXI-Stream == AXI-Stream
This is https://zipcpu.com/doc/axi-stream.pdf[AMBA 4 AXI4-Stream], minus several This is https://zipcpu.com/doc/axi-stream.pdf[AMBA 4 AXI4-Stream], minus several
signals. Generally, `ARESETn`, `TSTRB`, `TKEEP`, `TID`, `TDEST` are ommitted. signals. Generally, `ARESETn`, `TSTRB`, `TKEEP`, `TID`, `TDEST` are omitted.
Sometimes `TUSER` is omitted as well. Additionally, the `A` and `T` prefixes Sometimes `TUSER` is omitted as well. Additionally, the `A` and `T` prefixes
are not used. are not used. When the `user` signal is present, it generally indicates that the
associated data is erronious.
== Wishbone == Wishbone
This is https://cdn.opencores.org/downloads/wbspec_b4.pdf[Wishbone B4] in This is https://cdn.opencores.org/downloads/wbspec_b4.pdf[Wishbone B4] in
non-pipelined mode. Generally, `RST`, `TGA`, `TGC`, `TGD`, `RTY`, `SEL`, and non-pipelined ("`classic`") mode. This imposes a performance penalty on the bus,
`LOCK` signals are omitted. The `_I` and `_O` suffixes are not used. `DAT` is but wishbone is just used for management registers so I am not too concerned.
named `data_read` or `data_write`, depending on the direction of transfer. `ADR` Generally, `RST`, `TGA`, `TGC`, `TGD`, `RTY`, `SEL`, and `LOCK` signals are
is expanded to `addr`. omitted. The `_I` and `_O` suffixes are not used. `DAT` is named `data_read` or
`data_write`, depending on the direction of transfer. `ADR` is expanded to
`addr`. All cores have 16-bit ports with 16-bit granularity.