From 11bb9651c08ba862042eeb338089897dad30a441 Mon Sep 17 00:00:00 2001
From: Sean Anderson <seanga2@gmail.com>
Date: Fri, 13 Jan 2023 23:13:12 -0500
Subject: [PATCH] Use separate process for non-resetting registers

Including registers which are not reset in an asynchronous reset process
causes active-low clock-enable flip-flops to be synthesized. This is an
unusual configuration, incurs overhead, and isn't what we wanted to do
anyway. Use a separate process.

While we're at it, sort the bottom half of the if to match the top.

Fixes: 19f2f65 ("axis_mii_tx: Add reset")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
---
 rtl/axis_mii_tx.v        | 23 +++++++++++++----------
 rtl/axis_replay_buffer.v | 12 ++++++------
 2 files changed, 19 insertions(+), 16 deletions(-)

diff --git a/rtl/axis_mii_tx.v b/rtl/axis_mii_tx.v
index 02cebd9..4c50d74 100644
--- a/rtl/axis_mii_tx.v
+++ b/rtl/axis_mii_tx.v
@@ -502,6 +502,14 @@ module axis_mii_tx (
 		endcase
 	end
 
+	always @(posedge clk) begin
+		do_crc <= do_crc_next;
+		data <= data_next;
+		backoff <= backoff_next;
+		crc_state <= crc_state_next;
+		collision <= collision_next;
+	end
+
 	always @(posedge clk, posedge rst) begin
 		if (rst) begin
 			mii_tx_counter <= MII_100_RATIO;
@@ -524,30 +532,25 @@ module axis_mii_tx (
 			done <= 0;
 			replay <= 0;
 		end else begin
+			mii_tx_counter <= mii_tx_counter_next;
 			mii_tx_ce <= mii_tx_ce_next;
 			mii_tx_ce_next <= mii_tx_ce_next_next;
 			mii_tx_ce_next_next <= mii_tx_ce_next_next_next;
-			mii_tx_counter <= mii_tx_counter_next;
 			mii_tx_en <= mii_tx_en_next;
 			mii_txd <= odd_next ? data_next[7:4] : data_next[3:0];
-			do_crc <= do_crc_next;
 			odd <= odd_next;
 			state <= state_next;
 			state_counter <= state_counter_next;
-			buf_ready <= buf_ready_next;
-			err <= err_next;
-			data <= data_next;
-			replay <= replay_next;
-			done <= done_next;
 			retries <= retries_next;
-			backoff <= backoff_next;
 			lfsr <= lfsr_next;
-			crc_state <= crc_state_next;
-			collision <= collision_next;
 			transmit_ok <= transmit_ok_next;
 			gave_up <= gave_up_next;
 			late_collision <= late_collision_next;
 			underflow <= underflow_next;
+			buf_ready <= buf_ready_next;
+			err <= err_next;
+			done <= done_next;
+			replay <= replay_next;
 		end
 	end
 
diff --git a/rtl/axis_replay_buffer.v b/rtl/axis_replay_buffer.v
index 00fb856..8b5f080 100644
--- a/rtl/axis_replay_buffer.v
+++ b/rtl/axis_replay_buffer.v
@@ -144,6 +144,8 @@ module axis_replay_buffer (
 			buffer[s_ptr[BUF_WIDTH - 1:0]] <= { s_axis_data_last };
 		if (re)
 			{ m_axis_data } <= buffer[m_ptr[BUF_WIDTH - 1:0]];
+		last_ptr <= last_ptr_next;
+		s_axis_data_last <= s_axis_data;
 	end
 
 	always @(posedge clk, posedge rst) begin
@@ -159,18 +161,16 @@ module axis_replay_buffer (
 			m_axis_last <= 0;
 			sent_last <= 0;
 		end else begin
-			s_axis_data_last <= s_axis_data;
+			m_ptr <= m_ptr_next;
+			s_ptr <= s_ptr_next;
+			last <= last_next;
+			replayable <= replayable_next;
 			s_axis_valid_last <= s_axis_valid;
 			s_axis_last_last <= s_axis_last;
 			s_axis_ready <= s_axis_ready_next;
 			m_axis_last <= m_axis_last_next;
 			m_axis_valid <= m_axis_valid_next;
 			sent_last <= sent_last_next;
-			m_ptr <= m_ptr_next;
-			s_ptr <= s_ptr_next;
-			last <= last_next;
-			last_ptr <= last_ptr_next;
-			replayable <= replayable_next;
 		end
 	end