From 03715d4a8311bed6c12241099ca94529cc576fbe Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 6 Aug 2022 22:08:09 -0400 Subject: [PATCH] pcs: rx: Only flush on state change The PCS state machine is evaluated every cycle, but its outputs are only registers when the rx_bits module indicates. However, the flush signal is not registered and is instead combinatorial. Although it's OK to evaluate the other outputs every cycle, we should only indicate if we are actually going to change state. Fixes: d351291 ("Initial commit") Signed-off-by: Sean Anderson --- rtl/pcs.v | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/rtl/pcs.v b/rtl/pcs.v index 216f6a1..250de08 100644 --- a/rtl/pcs.v +++ b/rtl/pcs.v @@ -395,9 +395,9 @@ module pcs_rx_bits ( end /* - * If we are flushing flush then activity is based on stale - * data. Ignore it so we don't accidentally detect activity for - * data we are going to flush anyway. + * If we are flushing then activity is based on stale data. + * Ignore it so we don't accidentally detect activity for data + * we are going to flush anyway. */ if (flush) activity_next = 0; @@ -491,6 +491,11 @@ module pcs_rx ( endcase start = 0; + /* + * XXX: flush (unlike everything else here) is combinatorial; + * we should only flush if we are actually evaluating the + * state. + */ flush = 0; rx_next = rx; ce_next = indicate; @@ -560,7 +565,8 @@ end ; `CODE_T: if (aligned[4:0] == `CODE_R) begin - flush = 1; + if (indicate) + flush = 1; state_next = IDLE; valid_next = 0; end else begin