ethernet/rtl/common.vh

// SPDX-License-Identifier: AGPL-3.0-Only
/*
 * Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>
 */

`ifndef COMMON_VH
`define COMMON_VH

`default_nettype none
`timescale 1ns/1ns

`endif /* COMMON_VH */
Initial commit 2022-05-15 21:52:26 -05:00			`// SPDX-License-Identifier: AGPL-3.0-Only`
			`/*`
			`* Copyright (C) 2022 Sean Anderson <seanga2@gmail.com>`
			`*/`

			`ifndef COMMON_VH
			`define COMMON_VH

Move default_nettype/timescale declaration to common.vh We will need this in every verilog file, so consolidate things a bit. In terms of timescale, we need to modify the post-synthesis verilog generation a bit in order to avoid the module's timecale being inadverdently overwritten. Signed-off-by: Sean Anderson <seanga2@gmail.com> 2022-08-21 11:41:19 -05:00			`default_nettype none
			`timescale 1ns/1ns

Initial commit 2022-05-15 21:52:26 -05:00			`endif /* COMMON_VH */