ethernet/.gitignore

# build artifacts
*.vvp
*.blif
*.d
*.json
*.asc
*.synth.v
*.place.v
*.sdf
*.bin
log
tags

# test artifacts
__pycache__
*.pyc
.coverage
*.fst
results.xml
test_profile.pstat

# doc artifacts
*.html
Initial commit 2022-05-15 21:52:26 -05:00			`# build artifacts`
			`*.vvp`
			`*.blif`
			`*.d`
			`*.json`
			`*.asc`
Add some more files to gitignore Some of the ignores were not updated properly when reworking the Makefile. Also add tags. Fixes: 6af697b ("Initial support for post-placement simulation") Signed-off-by: Sean Anderson <seanga2@gmail.com> 2022-11-05 11:52:57 -05:00			`*.synth.v`
			`*.place.v`
			`*.sdf`
Add .bin to file extensions Clean up/ignore .bin files. Fixes: 5cf02e9 ("Support building actual bitstreams") Signed-off-by: Sean Anderson <seanga2@gmail.com> 2023-02-20 17:54:25 -06:00			`*.bin`
Clean/ignore log directory Clean out the log directory like the rest, and ignore it in git. Signed-off-by: Sean Anderson <seanga2@gmail.com> 2022-11-05 11:06:01 -05:00			`log`
Add some more files to gitignore Some of the ignores were not updated properly when reworking the Makefile. Also add tags. Fixes: 6af697b ("Initial support for post-placement simulation") Signed-off-by: Sean Anderson <seanga2@gmail.com> 2022-11-05 11:52:57 -05:00			`tags`
Initial commit 2022-05-15 21:52:26 -05:00
			`# test artifacts`
			`__pycache__`
			`*.pyc`
			`.coverage`
			`*.fst`
			`results.xml`
			`test_profile.pstat`
Add AXIS-Wishbone bridge This adds the core of the UART-Wishbone bridge. The protocol has a variable-length address phase to help reduce overhead. Multiple in-flight commands are not supported, although this could be resolved with some FIFOs. Signed-off-by: Sean Anderson <seanga2@gmail.com> 2023-03-01 18:14:59 -06:00
			`# doc artifacts`
			`*.html`