riscv

riscv synced new reference mmicko/sim_memory to riscv/yosys from mirror 2022-05-04 10:50:11 -05:00

riscv synced and deleted reference binder at riscv/OpenFPGA from mirror 2022-05-04 02:50:17 -05:00

riscv synced and deleted reference dependabot/submodules/yosys-plugins-f79f203 at riscv/OpenFPGA from mirror 2022-05-04 02:50:17 -05:00

riscv synced commits to master at riscv/OpenFPGA from mirror 2022-05-04 02:50:17 -05:00

f046224e5f Merge pull request #637 from lnis-uofu/binder

53f2335496 Merge branch 'master' into binder

d5716a2a8e Merge pull request #636 from lnis-uofu/dependabot/submodules/yosys-plugins-f79f203

882a620578 Merge branch 'master' into binder

d7f343552e Merge pull request #638 from lnis-uofu/patch_update

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riscv synced commits to binder at riscv/OpenFPGA from mirror 2022-05-03 18:40:17 -05:00

riscv synced new reference binder to riscv/OpenFPGA from mirror 2022-05-03 18:40:17 -05:00

riscv synced and deleted reference gpio_defaults_fix at riscv/caravel from mirror 2022-05-03 18:40:15 -05:00

riscv synced commits to main at riscv/caravel from mirror 2022-05-03 18:40:15 -05:00

6cfedf89a2 fixed caravel netlist to use the 1803 defaults block (#94)

riscv synced commits to master at riscv/OpenFPGA from mirror 2022-05-03 02:20:17 -05:00

e8a261452f Merge pull request #635 from lnis-uofu/binder

21c3dbf611 Added regression for template project

42567d8178 Updated docuementation

9891e42f7a Added template task

f12cf9c461 Adding binder enhancemens

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riscv synced commits to vpr_integration at riscv/OpenFPGA from mirror 2022-05-03 02:20:17 -05:00

cc7a91e7a7 Build rr node indices at top level tileable graph builder.

riscv synced and deleted reference binder at riscv/OpenFPGA from mirror 2022-05-03 02:20:16 -05:00

riscv synced commits to dependabot/submodules/yosys-plugins-f79f203 at riscv/OpenFPGA from mirror 2022-05-03 02:20:16 -05:00

riscv synced new reference dependabot/submodules/yosys-plugins-f79f203 to riscv/OpenFPGA from mirror 2022-05-03 02:20:16 -05:00

riscv synced commits to master at riscv/yosys from mirror 2022-05-03 02:10:11 -05:00

11e75bc27c Bump version

riscv synced new reference binder to riscv/OpenFPGA from mirror 2022-05-02 18:10:17 -05:00

riscv synced commits to binder at riscv/OpenFPGA from mirror 2022-05-02 18:10:16 -05:00

riscv synced commits to master at riscv/yosys from mirror 2022-05-02 09:50:10 -05:00

3730db4b98 AIM file could have gaps in or between inputs and inits

riscv synced and deleted reference binder at riscv/OpenFPGA from mirror 2022-05-02 01:50:17 -05:00

riscv synced commits to ganesh_dev at riscv/OpenFPGA from mirror 2022-05-02 01:50:17 -05:00

6358d25221 Merge branch 'master' into ganesh_dev

4a1a1b503d Merge pull request #632 from lnis-uofu/binder

928b6b834d Merge branch 'master' into binder

420714d22a Merge pull request #633 from lnis-uofu/patch_update

ce35e3a8d8 Updated Patch Count

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riscv synced commits to master at riscv/OpenFPGA from mirror 2022-05-02 01:50:17 -05:00

4a1a1b503d Merge pull request #632 from lnis-uofu/binder

928b6b834d Merge branch 'master' into binder

872d0d352e Merge remote-tracking branch 'origin/master' into binder

99a2d6d2da Updated readme

bbfcb61330 Added Binder interface

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