riscv
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  • Joined on 2021-05-24
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riscv synced commits to master at riscv/yosys from mirror 2022-05-09 05:10:11 -05:00
d562bfd165 Next dev cycle
6f9602b4cf Release version 0.17
72d2efeb32 Update CHANGELOG
65f70b9d50 Update manual
58b23954e8 Merge pull request #3299 from YosysHQ/mmicko/sim_memory
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riscv synced commits to refs/tags/yosys-0.17 at riscv/yosys from mirror 2022-05-09 05:10:11 -05:00
riscv synced new reference refs/tags/yosys-0.17 to riscv/yosys from mirror 2022-05-09 05:10:11 -05:00
riscv synced commits to binder at riscv/OpenFPGA from mirror 2022-05-08 21:10:17 -05:00
riscv synced new reference binder to riscv/OpenFPGA from mirror 2022-05-08 21:10:17 -05:00
riscv synced and deleted reference patch_update at riscv/OpenFPGA from mirror 2022-05-08 04:50:16 -05:00
riscv synced commits to master at riscv/OpenFPGA from mirror 2022-05-08 04:50:16 -05:00
6343082633 Merge pull request #646 from lnis-uofu/patch_update
5c51eef9a0 Updated Patch Count
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riscv synced commits to patch_update at riscv/OpenFPGA from mirror 2022-05-07 20:40:16 -05:00
riscv synced new reference patch_update to riscv/OpenFPGA from mirror 2022-05-07 20:40:16 -05:00
riscv synced and deleted reference mwk/opt-mem-lane at riscv/yosys from mirror 2022-05-07 20:30:10 -05:00
riscv synced commits to master at riscv/yosys from mirror 2022-05-07 20:30:10 -05:00
9c69e9f8a6 Bump version
77b1dfd8c3 opt_mem: Remove constant-value bit lanes.
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riscv synced commits to mwk/opt-mem-lane at riscv/yosys from mirror 2022-05-07 12:20:10 -05:00
a540354404 opt_mem: Remove constant-value bit lanes.
ccca4a8a4b opt_mem: Remove constant-value bit lanes.
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riscv synced and deleted reference binder at riscv/OpenFPGA from mirror 2022-05-07 04:20:17 -05:00
riscv synced and deleted reference dependabot/submodules/yosys-plugins-cfd794b at riscv/OpenFPGA from mirror 2022-05-07 04:20:17 -05:00
riscv synced and deleted reference patch_update at riscv/OpenFPGA from mirror 2022-05-07 04:20:17 -05:00
riscv synced commits to master at riscv/OpenFPGA from mirror 2022-05-07 04:20:17 -05:00
4c871dae42 Merge pull request #643 from lnis-uofu/binder
915935c72b Merge branch 'master' into binder
522982c9ba Adde vtr_benchmarks_template for demo
939e093b01 Merge pull request #641 from lnis-uofu/dependabot/submodules/yosys-plugins-cfd794b
c5642df68a Merge pull request #644 from lnis-uofu/patch_update
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riscv synced commits to binder at riscv/OpenFPGA from mirror 2022-05-06 20:10:17 -05:00
9473523b6b Added VTR arch without fracturable lut
fe29076ca5 Merge remote-tracking branch 'origin/master' into binder
bd162d94d7 Merge pull request #642 from lnis-uofu/gg_ci_cd_dev
275cda081e [Bugfix] Typo
e845b62322 Update regession tasks
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riscv synced commits to patch_update at riscv/OpenFPGA from mirror 2022-05-06 20:10:17 -05:00
riscv synced new reference patch_update to riscv/OpenFPGA from mirror 2022-05-06 20:10:17 -05:00
riscv synced commits to mwk/opt-mem-lane at riscv/yosys from mirror 2022-05-06 20:00:11 -05:00