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fd05f73d50
yosys
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backends
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verilog
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Akash Levy
ace558e90c
Simplify using module->ports, which is apparently sorted
2024-11-17 11:36:30 -08:00
..
Makefile.inc
initial import
2013-01-05 11:13:26 +01:00
verilog_backend.cc
Simplify using module->ports, which is apparently sorted
2024-11-17 11:36:30 -08:00