mirror of https://github.com/YosysHQ/yosys.git
79 lines
1.7 KiB
Verilog
79 lines
1.7 KiB
Verilog
`default_nettype none
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module nonblocking_gate (clk, ctrl, din, sel, dout);
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input wire clk;
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input wire [4:0] ctrl;
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input wire [1:0] din;
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input wire [0:0] sel;
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output reg [31:0] dout;
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always @(posedge clk)
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begin
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dout <= (dout)+(1);
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case (({(ctrl)*(sel)})+(0))
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0:
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dout[31:0] <= din;
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1:
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dout[31:1] <= din;
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2:
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dout[31:2] <= din;
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3:
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dout[31:3] <= din;
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4:
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dout[31:4] <= din;
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5:
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dout[31:5] <= din;
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6:
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dout[31:6] <= din;
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7:
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dout[31:7] <= din;
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8:
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dout[31:8] <= din;
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9:
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dout[31:9] <= din;
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10:
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dout[31:10] <= din;
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11:
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dout[31:11] <= din;
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12:
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dout[31:12] <= din;
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13:
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dout[31:13] <= din;
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14:
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dout[31:14] <= din;
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15:
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dout[31:15] <= din;
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16:
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dout[31:16] <= din;
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17:
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dout[31:17] <= din;
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18:
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dout[31:18] <= din;
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19:
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dout[31:19] <= din;
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20:
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dout[31:20] <= din;
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21:
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dout[31:21] <= din;
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22:
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dout[31:22] <= din;
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23:
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dout[31:23] <= din;
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24:
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dout[31:24] <= din;
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25:
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dout[31:25] <= din;
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26:
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dout[31:26] <= din;
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27:
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dout[31:27] <= din;
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28:
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dout[31:28] <= din;
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29:
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dout[31:29] <= din;
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30:
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dout[31:30] <= din;
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31:
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dout[31:31] <= din;
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endcase
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end
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endmodule
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