.. |
Makefile.inc
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nexus: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |
arith_map.v
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nexus: Fix arith_map CO signal.
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2022-02-06 13:05:30 +01:00 |
brams.txt
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nexus: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |
brams_map.v
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nexus: Fix BRAM write enable in PDP mode
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2023-01-04 17:59:36 +01:00 |
cells_map.v
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iopadmap: Add native support for negative-polarity output enable.
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2021-11-09 15:40:16 +01:00 |
cells_sim.v
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nexus: Fix BB sim model
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2022-01-19 18:14:24 +00:00 |
cells_xtra.py
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nexus: Add DSP simulation model
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2020-11-18 10:21:17 +00:00 |
cells_xtra.v
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nexus: Add DSP simulation model
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2020-11-18 10:21:17 +00:00 |
dsp_map.v
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nexus: DSP inference support
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2020-11-20 08:45:55 +00:00 |
latches_map.v
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synth_nexus: Initial implementation
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2020-10-15 08:52:15 +01:00 |
lrams.txt
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nexus: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |
lrams_map.v
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nexus: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |
lutrams.txt
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nexus: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |
lutrams_map.v
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nexus: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |
parse_init.vh
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synth_nexus: Initial implementation
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2020-10-15 08:52:15 +01:00 |
synth_nexus.cc
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nexus: Use `memory_libmap` pass.
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2022-05-18 17:32:56 +02:00 |