mirror of https://github.com/YosysHQ/yosys.git
27 lines
446 B
Plaintext
27 lines
446 B
Plaintext
read_verilog -icells opt_rmdff.v
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prep
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design -stash gold
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read_verilog -icells opt_rmdff.v
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proc
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opt_rmdff
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select -assert-count 0 c:remove*
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select -assert-min 7 c:keep*
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select -assert-count 0 t:$dffe 7:$_DFFE_* %u c:noenable* %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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equiv_make gold gate equiv
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hierarchy -top equiv
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equiv_simple -undef
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equiv_status -assert
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design -load gold
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stat
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design -load gate
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stat
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