mirror of https://github.com/YosysHQ/yosys.git
95 lines
1.6 KiB
Verilog
95 lines
1.6 KiB
Verilog
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module gen_test1(clk, a, b, y);
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input clk;
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input [7:0] a, b;
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output reg [7:0] y;
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genvar i, j;
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wire [15:0] tmp1;
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generate
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for (i = 0; i < 8; i = i + 1) begin:gen1
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wire and_wire, or_wire;
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assign and_wire = a[i] & b[i];
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assign or_wire = a[i] | b[i];
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if (i % 2 == 0) begin:gen2true
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assign tmp1[i] = and_wire;
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assign tmp1[i+8] = or_wire;
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end else begin:gen2false
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assign tmp1[i] = or_wire;
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assign tmp1[i+8] = and_wire;
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end
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end
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for (i = 0; i < 8; i = i + 1) begin:gen3
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wire [4:0] tmp2;
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for (j = 0; j <= 4; j = j + 1) begin:gen4
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wire tmpbuf;
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assign tmpbuf = tmp1[i+2*j];
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assign tmp2[j] = tmpbuf;
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end
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always @(posedge clk)
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y[i] <= ^tmp2;
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end
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endgenerate
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endmodule
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// ------------------------------------------
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module gen_test2(clk, a, b, y);
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input clk;
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input [7:0] a, b;
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output reg [8:0] y;
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integer i;
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reg [8:0] carry;
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always @(posedge clk) begin
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carry[0] = 0;
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for (i = 0; i < 8; i = i + 1) begin
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casez ({a[i], b[i], carry[i]})
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3'b?11, 3'b1?1, 3'b11?:
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carry[i+1] = 1;
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default:
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carry[i+1] = 0;
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endcase
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y[i] = a[i] ^ b[i] ^ carry[i];
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end
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y[8] = carry[8];
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end
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endmodule
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// ------------------------------------------
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module gen_test3(a, b, sel, y, z);
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input [3:0] a, b;
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input sel;
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output [3:0] y, z;
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genvar i;
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generate
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for (i=0; i < 2; i=i+1)
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assign y[i] = sel ? a[i] : b[i], z[i] = sel ? b[i] : a[i];
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for (i=0; i < 2; i=i+1) begin
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if (i == 0)
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assign y[2] = sel ? a[2] : b[2];
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else
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assign z[2] = sel ? a[2] : b[2];
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case (i)
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default:
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assign z[3] = sel ? a[3] : b[3];
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0:
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assign y[3] = sel ? a[3] : b[3];
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endcase
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end
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endgenerate
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endmodule
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