This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
f9dc1a2184
yosys
/
docs
/
source
/
APPNOTE_011_Design_Investig...
/
cmos.v
4 lines
74 B
Verilog
Raw
Blame
History
module
cmos_demo
(
input
a
,
b
,
output
[
1
:
0
]
y
)
;
assign
y
=
a
+
b
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink