mirror of https://github.com/YosysHQ/yosys.git
239 lines
6.9 KiB
C++
239 lines
6.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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template<class T> bool includes(const T &lhs, const T &rhs) {
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return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
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}
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#include "passes/pmgen/ice40_dsp_pm.h"
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void create_ice40_dsp(ice40_dsp_pm &pm)
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{
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auto &st = pm.st_ice40_dsp;
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#if 1
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log("\n");
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log("ffA: %s\n", log_id(st.ffA, "--"));
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log("ffB: %s\n", log_id(st.ffB, "--"));
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log("mul: %s\n", log_id(st.mul, "--"));
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log("ffY: %s\n", log_id(st.ffY, "--"));
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log("addAB: %s\n", log_id(st.addAB, "--"));
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log("muxAB: %s\n", log_id(st.muxAB, "--"));
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log("ffS: %s\n", log_id(st.ffS, "--"));
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#endif
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log("Checking %s.%s for iCE40 DSP inference.\n", log_id(pm.module), log_id(st.mul));
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if (GetSize(st.sigA) > 16) {
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log(" input A (%s) is too large (%d > 16).\n", log_signal(st.sigA), GetSize(st.sigA));
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return;
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}
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if (GetSize(st.sigB) > 16) {
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log(" input B (%s) is too large (%d > 16).\n", log_signal(st.sigB), GetSize(st.sigB));
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return;
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}
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if (GetSize(st.sigS) > 32) {
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log(" accumulator (%s) is too large (%d > 32).\n", log_signal(st.sigS), GetSize(st.sigS));
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return;
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}
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if (GetSize(st.sigY) > 32) {
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log(" output (%s) is too large (%d > 32).\n", log_signal(st.sigY), GetSize(st.sigY));
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return;
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}
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log(" replacing %s with SB_MAC16 cell.\n", log_id(st.mul->type));
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Cell *cell = pm.module->addCell(NEW_ID, "\\SB_MAC16");
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pm.module->swap_names(cell, st.mul);
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// SB_MAC16 Input Interface
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bool a_signed = st.mul->getParam("\\A_SIGNED").as_bool();
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bool b_signed = st.mul->getParam("\\B_SIGNED").as_bool();
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SigSpec A = st.sigA;
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A.extend_u0(16, a_signed);
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SigSpec B = st.sigB;
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B.extend_u0(16, b_signed);
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SigSpec CD;
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if (st.muxA)
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CD = st.muxA->getPort("\\B");
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if (st.muxB)
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CD = st.muxB->getPort("\\A");
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CD.extend_u0(32, a_signed && b_signed);
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cell->setPort("\\A", A);
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cell->setPort("\\B", B);
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cell->setPort("\\C", CD.extract(0, 16));
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cell->setPort("\\D", CD.extract(16, 16));
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cell->setParam("\\A_REG", st.ffA ? State::S1 : State::S0);
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cell->setParam("\\B_REG", st.ffB ? State::S1 : State::S0);
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cell->setPort("\\AHOLD", State::S0);
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cell->setPort("\\BHOLD", State::S0);
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cell->setPort("\\CHOLD", State::S0);
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cell->setPort("\\DHOLD", State::S0);
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cell->setPort("\\IRSTTOP", State::S0);
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cell->setPort("\\IRSTBOT", State::S0);
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if (st.clock != SigBit())
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{
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cell->setPort("\\CLK", st.clock);
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cell->setPort("\\CE", State::S1);
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cell->setParam("\\NEG_TRIGGER", st.clock_pol ? State::S0 : State::S1);
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log(" clock: %s (%s)", log_signal(st.clock), st.clock_pol ? "posedge" : "negedge");
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if (st.ffA)
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log(" ffA:%s", log_id(st.ffA));
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if (st.ffB)
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log(" ffB:%s", log_id(st.ffB));
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if (st.ffY)
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log(" ffY:%s", log_id(st.ffY));
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if (st.ffS)
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log(" ffS:%s", log_id(st.ffS));
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log("\n");
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}
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else
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{
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cell->setPort("\\CLK", State::S0);
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cell->setPort("\\CE", State::S0);
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cell->setParam("\\NEG_TRIGGER", State::S0);
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}
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// SB_MAC16 Cascade Interface
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cell->setPort("\\SIGNEXTIN", State::Sx);
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cell->setPort("\\SIGNEXTOUT", pm.module->addWire(NEW_ID));
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cell->setPort("\\CI", State::Sx);
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cell->setPort("\\CO", pm.module->addWire(NEW_ID));
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cell->setPort("\\ACCUMCI", State::Sx);
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cell->setPort("\\ACCUMCO", pm.module->addWire(NEW_ID));
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// SB_MAC16 Output Interface
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SigSpec O = st.ffS ? st.sigS : st.sigY;
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if (GetSize(O) < 32)
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O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
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cell->setPort("\\O", O);
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if (st.addAB) {
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log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
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cell->setPort("\\ADDSUBTOP", st.addAB->type == "$add" ? State::S0 : State::S1);
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cell->setPort("\\ADDSUBBOT", st.addAB->type == "$add" ? State::S0 : State::S1);
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} else {
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cell->setPort("\\ADDSUBTOP", State::S0);
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cell->setPort("\\ADDSUBBOT", State::S0);
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}
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cell->setPort("\\ORSTTOP", State::S0);
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cell->setPort("\\ORSTBOT", State::S0);
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cell->setPort("\\OHOLDTOP", State::S0);
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cell->setPort("\\OHOLDBOT", State::S0);
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SigSpec acc_reset = State::S0;
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if (st.muxA)
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acc_reset = st.muxA->getPort("\\S");
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if (st.muxB)
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acc_reset = pm.module->Not(NEW_ID, st.muxB->getPort("\\S"));
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cell->setPort("\\OLOADTOP", acc_reset);
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cell->setPort("\\OLOADBOT", acc_reset);
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// SB_MAC16 Remaining Parameters
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cell->setParam("\\C_REG", State::S0);
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cell->setParam("\\D_REG", State::S0);
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cell->setParam("\\TOP_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
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cell->setParam("\\BOT_8x8_MULT_REG", st.ffY ? State::S1 : State::S0);
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cell->setParam("\\PIPELINE_16x16_MULT_REG1", st.ffY ? State::S1 : State::S0);
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cell->setParam("\\PIPELINE_16x16_MULT_REG2", State::S0);
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cell->setParam("\\TOPOUTPUT_SELECT", Const(st.ffS ? 1 : 3, 2));
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cell->setParam("\\TOPADDSUB_LOWERINPUT", Const(2, 2));
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cell->setParam("\\TOPADDSUB_UPPERINPUT", State::S0);
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cell->setParam("\\TOPADDSUB_CARRYSELECT", Const(3, 2));
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cell->setParam("\\BOTOUTPUT_SELECT", Const(st.ffS ? 1 : 3, 2));
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cell->setParam("\\BOTADDSUB_LOWERINPUT", Const(2, 2));
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cell->setParam("\\BOTADDSUB_UPPERINPUT", State::S0);
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cell->setParam("\\BOTADDSUB_CARRYSELECT", Const(0, 2));
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cell->setParam("\\MODE_8x8", State::S0);
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cell->setParam("\\A_SIGNED", a_signed);
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cell->setParam("\\B_SIGNED", b_signed);
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pm.autoremove(st.mul);
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pm.autoremove(st.ffY);
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pm.autoremove(st.ffS);
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}
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struct Ice40DspPass : public Pass {
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Ice40DspPass() : Pass("ice40_dsp", "iCE40: map multipliers") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" ice40_dsp [options] [selection]\n");
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log("\n");
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log("Map multipliers and multiply-accumulate blocks to iCE40 DSP resources.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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// if (args[argidx] == "-singleton") {
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// singleton_mode = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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ice40_dsp_pm(module, module->selected_cells()).run_ice40_dsp(create_ice40_dsp);
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}
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} Ice40DspPass;
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PRIVATE_NAMESPACE_END
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