mirror of https://github.com/YosysHQ/yosys.git
583 lines
17 KiB
C++
583 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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//get the list of cells hooked up to at least one bit of a given net
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pool<Cell*> get_other_cells(const RTLIL::SigSpec& port, ModIndex& index, Cell* src)
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{
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pool<Cell*> rval;
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for(auto b : port)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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for(auto x : ports)
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{
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if(x.cell == src)
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continue;
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rval.insert(x.cell);
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}
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}
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return rval;
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}
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//return true if there is a full-width bus connection from cell a port ap to cell b port bp
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//if other_conns_allowed is false, then we require a strict point to point connection (no other links)
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bool is_full_bus(
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const RTLIL::SigSpec& sig,
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ModIndex& index,
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Cell* a,
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RTLIL::IdString ap,
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Cell* b,
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RTLIL::IdString bp,
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bool other_conns_allowed = false)
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{
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for(auto s : sig)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(s);
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bool found_a = false;
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bool found_b = false;
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for(auto x : ports)
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{
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if( (x.cell == a) && (x.port == ap) )
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found_a = true;
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else if( (x.cell == b) && (x.port == bp) )
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found_b = true;
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else if(!other_conns_allowed)
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return false;
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}
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if( (!found_a) || (!found_b) )
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return false;
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}
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return true;
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}
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//return true if the signal connects to one port only (nothing on the other end)
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bool is_unconnected(const RTLIL::SigSpec& port, ModIndex& index)
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{
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for(auto b : port)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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if(ports.size() > 1)
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return false;
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}
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return true;
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}
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struct CounterExtraction
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{
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int width; //counter width
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RTLIL::Wire* rwire; //the register output
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bool has_reset; //true if we have a reset
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RTLIL::SigSpec rst; //reset pin
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int count_value; //value we count from
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RTLIL::SigSpec clk; //clock signal
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RTLIL::SigSpec outsig; //counter output signal
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RTLIL::Cell* count_mux; //counter mux
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RTLIL::Cell* count_reg; //counter register
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RTLIL::Cell* underflow_inv; //inverter reduction for output-underflow detect
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pool<ModIndex::PortInfo> pouts; //Ports that take a parallel output from us
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};
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//attempt to extract a counter centered on the given adder cell
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//For now we only support DOWN counters.
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//TODO: up/down support
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int counter_tryextract(
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ModIndex& index,
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Cell *cell,
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CounterExtraction& extract,
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pool<RTLIL::IdString>& parallel_cells,
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int maxwidth)
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{
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SigMap& sigmap = index.sigmap;
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//A counter with less than 2 bits makes no sense
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//TODO: configurable min threshold
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int a_width = cell->getParam("\\A_WIDTH").as_int();
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extract.width = a_width;
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if( (a_width < 2) || (a_width > maxwidth) )
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return 1;
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//Second input must be a single bit
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int b_width = cell->getParam("\\B_WIDTH").as_int();
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if(b_width != 1)
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return 2;
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//Both inputs must be unsigned, so don't extract anything with a signed input
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bool a_sign = cell->getParam("\\A_SIGNED").as_bool();
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bool b_sign = cell->getParam("\\B_SIGNED").as_bool();
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if(a_sign || b_sign)
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return 3;
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//To be a counter, one input of the ALU must be a constant 1
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//TODO: can A or B be swapped in synthesized RTL or is B always the 1?
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const RTLIL::SigSpec b_port = sigmap(cell->getPort("\\B"));
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if(!b_port.is_fully_const() || (b_port.as_int() != 1) )
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return 4;
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//BI and CI must be constant 1 as well
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const RTLIL::SigSpec bi_port = sigmap(cell->getPort("\\BI"));
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if(!bi_port.is_fully_const() || (bi_port.as_int() != 1) )
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return 5;
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const RTLIL::SigSpec ci_port = sigmap(cell->getPort("\\CI"));
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if(!ci_port.is_fully_const() || (ci_port.as_int() != 1) )
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return 6;
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//CO and X must be unconnected (exactly one connection to each port)
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if(!is_unconnected(sigmap(cell->getPort("\\CO")), index))
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return 7;
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if(!is_unconnected(sigmap(cell->getPort("\\X")), index))
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return 8;
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//Y must have exactly one connection, and it has to be a $mux cell.
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//We must have a direct bus connection from our Y to their A.
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const RTLIL::SigSpec aluy = sigmap(cell->getPort("\\Y"));
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pool<Cell*> y_loads = get_other_cells(aluy, index, cell);
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if(y_loads.size() != 1)
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return 9;
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Cell* count_mux = *y_loads.begin();
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extract.count_mux = count_mux;
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if(count_mux->type != "$mux")
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return 10;
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if(!is_full_bus(aluy, index, cell, "\\Y", count_mux, "\\A"))
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return 11;
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//B connection of the mux is our underflow value
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const RTLIL::SigSpec underflow = sigmap(count_mux->getPort("\\B"));
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if(!underflow.is_fully_const())
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return 12;
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extract.count_value = underflow.as_int();
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//S connection of the mux must come from an inverter (need not be the only load)
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const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort("\\S"));
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extract.outsig = muxsel;
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pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
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Cell* underflow_inv = NULL;
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for(auto c : muxsel_conns)
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{
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if(c->type != "$logic_not")
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continue;
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if(!is_full_bus(muxsel, index, c, "\\Y", count_mux, "\\S", true))
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continue;
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underflow_inv = c;
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break;
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}
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if(underflow_inv == NULL)
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return 13;
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extract.underflow_inv = underflow_inv;
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//Y connection of the mux must have exactly one load, the counter's internal register
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const RTLIL::SigSpec muxy = sigmap(count_mux->getPort("\\Y"));
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pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
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if(muxy_loads.size() != 1)
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return 14;
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Cell* count_reg = *muxy_loads.begin();
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extract.count_reg = count_reg;
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if(count_reg->type == "$dff")
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extract.has_reset = false;
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else if(count_reg->type == "$adff")
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{
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extract.has_reset = true;
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//Verify ARST_VALUE is zero and ARST_POLARITY is 1
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//TODO: infer an inverter to make it 1 if necessary, so we can support negative level resets?
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if(count_reg->getParam("\\ARST_POLARITY").as_int() != 1)
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return 22;
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if(count_reg->getParam("\\ARST_VALUE").as_int() != 0)
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return 23;
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//Save the reset
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extract.rst = sigmap(count_reg->getPort("\\ARST"));
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}
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//TODO: support synchronous reset
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else
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return 15;
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if(!is_full_bus(muxy, index, count_mux, "\\Y", count_reg, "\\D"))
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return 16;
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//TODO: Verify count_reg CLK_POLARITY is 1
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//Register output must have exactly two loads, the inverter and ALU
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//(unless we have a parallel output!)
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const RTLIL::SigSpec qport = count_reg->getPort("\\Q");
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const RTLIL::SigSpec cnout = sigmap(qport);
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pool<Cell*> cnout_loads = get_other_cells(cnout, index, count_reg);
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if(cnout_loads.size() > 2)
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{
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//If we specified a limited set of cells for parallel output, check that we only drive them
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if(!parallel_cells.empty())
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{
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for(auto c : cnout_loads)
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{
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if(c == underflow_inv)
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continue;
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if(c == cell)
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continue;
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//Make sure we're in the whitelist
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if( parallel_cells.find(c->type) == parallel_cells.end())
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return 17;
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//Figure out what port(s) are driven by it
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//TODO: this can probably be done more efficiently w/o multiple iterations over our whole net?
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RTLIL::IdString portname;
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for(auto b : qport)
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{
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pool<ModIndex::PortInfo> ports = index.query_ports(b);
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for(auto x : ports)
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{
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if(x.cell != c)
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continue;
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if(portname == "")
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portname = x.port;
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//somehow our counter output is going to multiple ports
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//this makes no sense, don't allow inference
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else if(portname != x.port)
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return 17;
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}
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}
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//Save the other loads
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extract.pouts.insert(ModIndex::PortInfo(c, portname, 0));
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}
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}
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}
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if(!is_full_bus(cnout, index, count_reg, "\\Q", underflow_inv, "\\A", true))
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return 18;
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if(!is_full_bus(cnout, index, count_reg, "\\Q", cell, "\\A", true))
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return 19;
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//Look up the clock from the register
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extract.clk = sigmap(count_reg->getPort("\\CLK"));
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//Register output net must have an INIT attribute equal to the count value
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extract.rwire = cnout.as_wire();
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if(extract.rwire->attributes.find("\\init") == extract.rwire->attributes.end())
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return 20;
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int rinit = extract.rwire->attributes["\\init"].as_int();
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if(rinit != extract.count_value)
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return 21;
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return 0;
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}
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void counter_worker(
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ModIndex& index,
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Cell *cell,
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unsigned int& total_counters,
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pool<Cell*>& cells_to_remove,
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pool<pair<Cell*, string>>& cells_to_rename,
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pool<RTLIL::IdString>& parallel_cells,
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int maxwidth)
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{
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SigMap& sigmap = index.sigmap;
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//Core of the counter must be an ALU
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if (cell->type != "$alu")
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return;
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//A input is the count value. Check if it has COUNT_EXTRACT set.
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//If it's not a wire, don't even try
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auto port = sigmap(cell->getPort("\\A"));
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if(!port.is_wire())
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return;
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RTLIL::Wire* a_wire = port.as_wire();
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bool force_extract = false;
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bool never_extract = false;
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string count_reg_src = a_wire->attributes["\\src"].decode_string().c_str();
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if(a_wire->attributes.find("\\COUNT_EXTRACT") != a_wire->attributes.end())
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{
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pool<string> sa = a_wire->get_strpool_attribute("\\COUNT_EXTRACT");
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string extract_value;
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if(sa.size() >= 1)
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{
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extract_value = *sa.begin();
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log(" Signal %s declared at %s has COUNT_EXTRACT = %s\n",
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log_id(a_wire),
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count_reg_src.c_str(),
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extract_value.c_str());
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if(extract_value == "FORCE")
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force_extract = true;
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else if(extract_value == "NO")
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never_extract = true;
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else if(extract_value == "AUTO")
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{} //default
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else
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log_error(" Illegal COUNT_EXTRACT value %s (must be one of FORCE, NO, AUTO)\n",
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extract_value.c_str());
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}
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}
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//If we're explicitly told not to extract, don't infer a counter
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if(never_extract)
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return;
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//Attempt to extract a counter
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CounterExtraction extract;
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int reason = counter_tryextract(index, cell, extract, parallel_cells, maxwidth);
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//Nonzero code - we could not find a matchable counter.
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//Do nothing, unless extraction was forced in which case give an error
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if(reason != 0)
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{
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static const char* reasons[24]=
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{
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"no problem", //0
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"counter is too large/small", //1
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"counter does not count by one", //2
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"counter uses signed math", //3
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"counter does not count by one", //4
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"ALU is not a subtractor", //5
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"ALU is not a subtractor", //6
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"ALU ports used outside counter", //7
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"ALU ports used outside counter", //8
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"ALU output used outside counter", //9
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"ALU output is not a mux", //10
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"ALU output is not full bus", //11
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"Underflow value is not constant", //12
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"No underflow detector found", //13
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"Mux output is used outside counter", //14
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"Counter reg is not DFF/ADFF", //15
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"Counter input is not full bus", //16
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"Count register is used outside counter, but not by an allowed cell", //17
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"Register output is not full bus", //18
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"Register output is not full bus", //19
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"No init value found", //20
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"Underflow value is not equal to init value", //21
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"Reset polarity is not positive", //22
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"Reset is not to zero" //23
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};
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if(force_extract)
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{
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log_error(
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"Counter extraction is set to FORCE on register %s, but a counter could not be inferred (%s)\n",
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log_id(a_wire),
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reasons[reason]);
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}
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return;
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}
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//Get new cell name
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string countname = string("$COUNTx$") + log_id(extract.rwire->name.str());
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//Wipe all of the old connections to the ALU
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cell->unsetPort("\\A");
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cell->unsetPort("\\B");
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cell->unsetPort("\\BI");
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cell->unsetPort("\\CI");
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cell->unsetPort("\\CO");
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cell->unsetPort("\\X");
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cell->unsetPort("\\Y");
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cell->unsetParam("\\A_SIGNED");
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cell->unsetParam("\\A_WIDTH");
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cell->unsetParam("\\B_SIGNED");
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cell->unsetParam("\\B_WIDTH");
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cell->unsetParam("\\Y_WIDTH");
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//Change the cell type
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cell->type = "$__COUNT_";
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//Hook up resets
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if(extract.has_reset)
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{
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//TODO: support other kinds of reset
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cell->setParam("\\RESET_MODE", RTLIL::Const("LEVEL"));
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cell->setPort("\\RST", extract.rst);
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}
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else
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{
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cell->setParam("\\RESET_MODE", RTLIL::Const("RISING"));
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cell->setPort("\\RST", RTLIL::SigSpec(false));
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}
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//Hook up other stuff
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//cell->setParam("\\CLKIN_DIVIDE", RTLIL::Const(1));
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cell->setParam("\\COUNT_TO", RTLIL::Const(extract.count_value));
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cell->setParam("\\WIDTH", RTLIL::Const(extract.width));
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cell->setPort("\\CLK", extract.clk);
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cell->setPort("\\OUT", extract.outsig);
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//Hook up hard-wired ports (for now CE and up/=down are not supported), default to no parallel output
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cell->setParam("\\HAS_POUT", RTLIL::Const(0));
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cell->setParam("\\HAS_CE", RTLIL::Const(0));
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cell->setParam("\\DIRECTION", RTLIL::Const("DOWN"));
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cell->setPort("\\CE", RTLIL::Const(1));
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cell->setPort("\\UP", RTLIL::Const(1));
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//Hook up any parallel outputs
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for(auto load : extract.pouts)
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{
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log(" Counter has parallel output to cell %s port %s\n", log_id(load.cell->name), log_id(load.port));
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//Find the wire hooked to the old port
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auto sig = load.cell->getPort(load.port);
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//Connect it to our parallel output
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//(this is OK to do more than once b/c they all go to the same place)
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cell->setPort("\\POUT", sig);
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cell->setParam("\\HAS_POUT", RTLIL::Const(1));
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}
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//Delete the cells we've replaced (let opt_clean handle deleting the now-redundant wires)
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cells_to_remove.insert(extract.count_mux);
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cells_to_remove.insert(extract.count_reg);
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cells_to_remove.insert(extract.underflow_inv);
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//Log it
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total_counters ++;
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string reset_type = "non-resettable";
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if(extract.has_reset)
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{
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//TODO: support other kind of reset
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reset_type = "async resettable";
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}
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log(" Found %d-bit %s down counter %s (counting from %d) for register %s declared at %s\n",
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extract.width,
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reset_type.c_str(),
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countname.c_str(),
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extract.count_value,
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log_id(extract.rwire->name),
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count_reg_src.c_str());
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//Optimize the counter
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//If we have no parallel output, and we have redundant bits, shrink us
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if(extract.pouts.empty())
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{
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//TODO: Need to update this when we add support for counters with nonzero reset values
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//to make sure the reset value fits in our bit space too
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//Optimize it
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int newbits = ceil(log2(extract.count_value));
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if(extract.width != newbits)
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{
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cell->setParam("\\WIDTH", RTLIL::Const(newbits));
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log(" Optimizing out %d unused high-order bits (new width is %d)\n",
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extract.width - newbits,
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newbits);
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}
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}
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//Finally, rename the cell
|
|
cells_to_rename.insert(pair<Cell*, string>(cell, countname));
|
|
}
|
|
|
|
struct ExtractCounterPass : public Pass {
|
|
ExtractCounterPass() : Pass("extract_counter", "Extract GreenPak4 counter cells") { }
|
|
virtual void help()
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" extract_counter [options] [selection]\n");
|
|
log("\n");
|
|
log("This pass converts non-resettable or async resettable down counters to\n");
|
|
log("counter cells. Use a target-specific 'techmap' map file to convert those cells\n");
|
|
log("to the actual target cells.\n");
|
|
log("\n");
|
|
log(" -maxwidth N\n");
|
|
log(" Only extract counters up to N bits wide\n");
|
|
log("\n");
|
|
log(" -pout X,Y,...\n");
|
|
log(" Only allow parallel output from the counter to the listed cell types\n");
|
|
log(" (if not specified, parallel outputs are not restricted)\n");
|
|
log("\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
|
{
|
|
log_header(design, "Executing EXTRACT_COUNTER pass (find counters in netlist).\n");
|
|
|
|
int maxwidth = 64;
|
|
size_t argidx;
|
|
pool<RTLIL::IdString> parallel_cells;
|
|
for (argidx = 1; argidx < args.size(); argidx++)
|
|
{
|
|
if (args[argidx] == "-pout")
|
|
{
|
|
if(argidx + 1 >= args.size())
|
|
{
|
|
log_error("extract_counter -pout requires an argument\n");
|
|
return;
|
|
}
|
|
|
|
std::string pouts = args[++argidx];
|
|
std::string tmp;
|
|
for(size_t i=0; i<pouts.length(); i++)
|
|
{
|
|
if(pouts[i] == ',')
|
|
{
|
|
parallel_cells.insert(RTLIL::escape_id(tmp));
|
|
tmp = "";
|
|
}
|
|
else
|
|
tmp += pouts[i];
|
|
}
|
|
parallel_cells.insert(RTLIL::escape_id(tmp));
|
|
continue;
|
|
}
|
|
|
|
if (args[argidx] == "-maxwidth" && argidx+1 < args.size())
|
|
{
|
|
maxwidth = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
//Extract all of the counters we could find
|
|
unsigned int total_counters = 0;
|
|
for (auto module : design->selected_modules())
|
|
{
|
|
pool<Cell*> cells_to_remove;
|
|
pool<pair<Cell*, string>> cells_to_rename;
|
|
|
|
ModIndex index(module);
|
|
for (auto cell : module->selected_cells())
|
|
counter_worker(index, cell, total_counters, cells_to_remove, cells_to_rename, parallel_cells, maxwidth);
|
|
|
|
for(auto cell : cells_to_remove)
|
|
{
|
|
//log("Removing cell %s\n", log_id(cell->name));
|
|
module->remove(cell);
|
|
}
|
|
|
|
for(auto cpair : cells_to_rename)
|
|
{
|
|
//log("Renaming cell %s to %s\n", log_id(cpair.first->name), cpair.second.c_str());
|
|
module->rename(cpair.first, cpair.second);
|
|
}
|
|
}
|
|
|
|
if(total_counters)
|
|
log("Extracted %u counters\n", total_counters);
|
|
}
|
|
} ExtractCounterPass;
|
|
|
|
PRIVATE_NAMESPACE_END
|